Secure-IC SAS 

Chiplets enable considerable gains in agility, scaling, and TTM. To unleash the full potential of this promise, it is required that the various chiplets be trusted in terms of provenance. An incorrect mix and match of inconsistent or even rogue chiplets would undermine the viability of the approach. Hence caring about cybersecurity is a prerequisite.

In this presentation, we adopt an analytical posture to address the question of System-in-Package (SiP) trustworthiness. We show that existing cybersecurity functions can be leveraged to emerge secure chiplets aggregation. We also demonstrate that the solution can be implemented as part of a reference chiplet architecture, as provided by Cadence Silicon Solution Group (SSG) / Compute Solutions Group (CSG).

The SiP will be trusted if two properties are safeguarded: Hardware & Software Bill of Material (HBOM and SBOM) secure provenance and integrity.

In a risk analysis approach, we MUST consider threat agents. Their exact nature and intentions are hard to predict exhaustively, but let us give some examples:

- Nation states attacks exploiting the supply chain;

- Incorrect HBOM or SBOM leading to configuration errors thereby voiding safety guarantees;

- Economic fraud abusing the chiplet business model, through supply of lower PPA chiplets or overbuilding.

For those reasons, security is a system-level overarching requirement.

It is mostly a cybersecurity (security orchestrated at logic level) topic, which nonetheless should be reinforced by a physical security dimension as attackers can procure chiplets from the open market to train their attacks (reconnaissance phase).

Cadence partners with Secure-IC to offer to their Customers the best-of-breed security solution, which has been proven suitable for chiplets.

It is backed on multicertified IPs and vetted cybersecurity concepts:

 - security by default, hence end-to-end security, from pre-silicon to mission mode, incl. through delegation

 - fail secure, i.e., whatever happens, the S500 solution does not compromise the security

 - resiliency: the system does not brick in case of an issue (bug or attack), but leave it possible for the user to recover through diagnose services

 - minimality of the design, to allow for agnosticity wrt use-cases

 - defense in depth (e.g., software no touch key, or Internal Key Generation)

 - capability to debug securely

 - capability to manage (multi-domain) power securely

 - pre-compliance by activating configuration items

Arm

The growing complexity of system-on-chip (SoC) designs and the demand for scalable, high-performance solutions have ushered in a new era of innovation with chiplets. We will explore the exciting opportunities unlocked by chiplet-based designs, emphasizing the need for collaboration to enable chiplet interoperability.

We will introduce the Arm Chiplet System Architecture (CSA), detailing its role in enabling modular, scalable designs that tackle challenges in performance, cost, and time-to-market. CSA enables greater reuse of components (physical design IP, soft IP etc) between multiple suppliers. It helps standardization efforts around system design choices for different chiplet types, such as how to partition an Arm-based system across multiple chiplets, or their high-level properties.

Cadence will highlight its successful chiplet tapeout, a compelling case study and the industry’s first Arm CSA-compliant base system chiplet, showcasing its capabilities and potential applications. We will discuss this scalable chiplet architecture and Cadence’s flexible engagement model that realizes the benefits of chiplets, including accelerated development cycles, greater levels of integration and improved system flexibility.

Join us to gain insights into how Arm and Cadence's collaboration is pushing the boundaries of semiconductor design, setting the stage for a future defined by smarter, more adaptable technologies.

Broadcom

Within the AI/ML accelerator "XPU" space there is a demand for extreme levels of advanced package integration to meet the ever expanding requirements of Large Language Models (LLM's) and Deep Learning Recommendation Models (DLRM's). For some time now, these XPU's have achieved this via leading-edge process nodes, maximum reticle field die sizes and heterogeneous chiplet integration using 2.5D based interposers. It became clear that the addition of 3D integration via die stacking came with features particularly well suited to these architectures.  The industry has begun to refer to this combination of advanced packaging techniques as "3.5D". The following talk gives some practical insights to the problems that 3.5D technology solves in this space as well as the challenges of integrating such large scale designs. The Cadence Integrity 3D-IC platform has been heavily used to implement a correct by construction floor planning and assembly flow that has allowed us to achieve first time right ASIC silicon. We will highlight the application of some of the key Integrity 3D-IC features in this talk.

Microsoft

Handling the data processing demands of cloud workloads needs enhanced high performance chiplet architecture designs. With modular chiplet designs , come complexities with system planning and implementation , along with verification of the designs at System Level. In this presentation, we will discuss multi chiplet design planning and multi-fabric verification, with focus on signal integrity (SI) and power integrity (PI) analysis flows developed across dies, interposers, and packages. Session with also talk about limitation with gds file into system analysis tool. Complexity in  translation causing the false alarm in analysis results. Other limitation is polygon shapes in GDS loses actual system intent. With  new Integrated direct cut in Construct we can easily work on in-design analysis and backannotated feedback into Integrity 3D-IC Construction framework. This Boots productivity and improve TAT during the chiplet construction stage compared with the traditional flow. The session will also cover how the design engineers can quickly and efficient enabled construct-analyze loop in turns. This enables quick closure in design cycle phase.

Cadence

Accommodating today’s chip design requirements within narrow market windows has led to a severe predictability crisis. Engineers are often faced with the challenge of determining design feasibility for larger, higher performance, power-hungry chips with incomplete netlists, libraries, and constraints. Additionally, there is no one single in-design solution that allows concurrent planning, assessment of floorplans across hierarchies for congestion, timing, and power without delving into real implementation. Deep sub-micron, complex integration guidelines for full chip assembly break the correlation with what top level planner sees vs block level implementation engineer leading to several design iterations and complex hand off across teams.

This presentation presents a novel end to end solution through a top-down hierarchical design methodology combined with an early physical “automatic” planning/prototyping solution, which significantly increases design productivity and restores schedule predictability across large physical hard IPs that dictate project TAT and convergence. Central to this approach is the use of the Early Floorplan Synthesis (EFS) cockpit, a powerful tool feature that allows engineers to concurrently tune the physical features of design subsystems and PPA (Power, Performance, and Area). This enables rapid evaluation and optimization of floorplans, addressing critical metrics such as congestion, timing, and power early in the design process with visibility across hierarchies executed by a single engineer.

By leveraging the EFS cockpit, engineers can proactively assess and refine design feasibility, ensuring that potential issues are identified and mitigated before moving into detailed implementation. This capability is crucial for managing the complexity of large chiplet IP subsystems, where early insights into physical characteristics and PPA can significantly impact the overall design quality and time-to-market.

This presentation showcases how the EFS cockpit integrates with the complete hierarchical design mode of work with real SSG IP design with 30m+ instances and how it enables rapid exploration, planning and concurrent execution, integration across hierarchy with one single Top Level Planner/Engineer eventually paving path for 3D/2.5 Design Hierarchy planning and co-optimization mode of work.

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

Samsung

This abstract presents an advanced methodology for power integrity (PI) analysis in 3D-IC integration, a crucial component in achieving higher performance, power efficiency, and system scalability in modern semiconductor technology. As the complexity of power delivery networks (PDNs) in 3D-IC architectures increases, challenges such as IR drop, electromigration (EM), and simultaneous switching noise (SSN) necessitate effective management to ensure reliable operation. Traditional 2D-IC PI techniques often fall short in addressing the vertical interactions and multi-die dependencies characteristic of 3D-IC designs.

We propose a comprehensive methodology for full-flow power integrity analysis, encompassing the entire design process from early exploration to final sign-off, employing Cadence's advanced EDA tools, including Voltus, Innovus, and Integrity 3D-IC. This innovative approach utilizes adaptive partitioning techniques, hierarchical modeling, and macro abstraction methods to enhance simulation accuracy and reduce the turnaround time (TAT) for electromigration and IR (EMIR) analysis.  Adaptive Partitioning for Efficient 3D-IC Simulation:

 - Partitioning Strategy: Groups dies with similar spatial areas into the same partition, effectively minimizing unnecessary iterations during simulation.

 - Simulation Efficiency: Reduces computational overhead while enhancing the convergence speed of power integrity analysis.

 XM-Based Hierarchical Modeling for Efficient 3D-IC EMIR Analysis:

 - High-Accuracy Macro Modeling: XM enables the creation of compact, reduced-order macro-models for individual blocks, dies, or chiplets.

 - Hierarchical Integration: Facilitates the efficient integration of block-level models into full-chip or system-level EMIR analysis without the need for re-simulation.

A case study of adaptive partitioning applied to Samsung Foundry's 2.5D advanced node design, which incorporates 100K bumps, achieves over a 10% reduction in EMIR simulation turnaround time with less than 5% accuracy loss. Additionally, another case study of XM-Based Hierarchical Modeling on Samsung Foundry's advanced node design illustrates remarkable efficiency, achieving over a 50% reduction in EMIR simulation turnaround time with less than 1% accuracy loss without package considerations and a 5% accuracy loss with package inclusion. Notably, the number of Power/Ground (PG) node counts to solve decreases from 5.8 billion in the flat case to 2.6 billion.

Samsung Semiconductor

What does it mean to “Shift Left & Stretch Right” when it comes to chiplet design?  It means the ability to start earlier and extend and leverage the work longer into the design process.  And how do we do this…a Digital Twin!

The integration of chiplets into semiconductor systems is transforming the landscape of microelectronics, promising enhanced modularity, scalability, and performance optimization.  To fully exploit these advantages, advanced methodologies for design, testing, and validation are crucial.  The digital twin technology in chiplet development proposes a framework that leverages virtual replicas to simulate, monitor, and optimize chiplet-based systems throughout their lifecycle.  The shift-left and stretch-right strategies are key in decoupling software and hardware development in system design.

By creating accurate digital models that mirror the physical chiplets, the framework facilitates early architecture exploration, performance benchmarking, and design refinement.  Embedded in continuous integration and continuous deployment processes, use cases for digital twins include early software development, regression testing, feature updates, and predictive maintenance.  We present a case study demonstrating how digital twins can be employed to streamline chiplet integration, reduce development cycles, and enhance system reliability, with a proven AI Accelerator to run inferencing and Vision DSPs to host AI accelerators and complemented by running partial networks, supporting pre/post processing and sensor fusion workloads on Samsung Foundry SF5A process node.  The digital twin technology can significantly improve the efficiency of chiplet development processes, offering a promising pathway for advancing semiconductor innovation.

Samsung India

Samsung Semiconductor India Research is an innovative powerhouse and believes in growing together by deploying industry leading cutting edge design methodologies. In this session, we will talk about how we have used Cadence Cerebrus AI Studio which is Industry’s first SoC design optimization platform using Advanced AI technology to achieve PPA improvement and engineering efficiency. We will also talk about how we leveraged multiple features offered by this tool like live design dashboard, advanced data analytics and Smart Model Selection for faster design convergence. 

Qualcomm 

With the ever-increasing demand for PPA optimization and multiple chip tape-outs happening in a short span, we need a tool that can deliver the best PPA with minimal user intervention by exploring design and tool options. As workloads increase, we also need a smart way to boost engineer productivity without compromising chip quality.

Cerebrus offers an excellent solution to these challenges by providing users with the flexibility to explore and fine-tune current PPA recipes. Its user-friendly model easily integrates into our existing flow, making it a push-button solution for executing designs. Its different operation modes, such as cold and warm start, provide tailored models for each design throughout the design cycle. On average, this model has achieved a 3-5% improvement in TNS and a 2-3% reduction in total power on high-performance CPU blocks with highly tuned power recipes (xReplay, GlitchOpt).

In this session, we will cover how to use the Cerebrus solution in the backend Innovus flow to achieve the best PPA for any block. We will explore various operation modes, including system primitive and user primitive modes.

Intel

The study examined the Cadence Machine learning algorithms along with the Floorplan exploration feature. This paper highlights the PPA improvements seen in various blocks, targeting dynamic and leakage power,TNS and area. 

Additionally, it focuses on the floorplan exploration feature which immensely helped in creating a robust baseline for efficient floorplan design.

This paper also details the implementation of the Warm-Start and Relay flows available in Cerebrus addressing clk latency, power, density targets which were are all vital in improving PPA.

IBM Research

Macro placement has become increasingly challenging for today's chip designers as modern ASIC SoCs grow more complex, integrating various third-party IPs to meet end-user requirements. The chip designers furthermore have to deal with numerous parameters in EDA tools making design flow optimization cumbersome. In this work, we demonstrate Cerebrus's capability to leverage AI-driven optimization and a massive cloud computing platform for parameter tuning and floorplan exploration. We first use Genus and Innovus for logic synthesis and physical implementation to establish baseline results for the open-source RISC-V design called BlackParrot. We then use Cerebrus to perform Power, Performance, and Area (PPA) optimization, refine the flow parameters for the baseline, and achieve an improved base-case scenario that reduces the WNS by 48%. We subsequently utilize Cerebrus' targeted application for floorplan optimization (FP-OPT) which adjusts the floorplan size and performs concurrent macro placement to improve the design timing further. The optimized floorplan from FP-OPT is reintegrated into the initial PPA optimization process. By combining PPA optimization with FP-OPT, we show that 80% WNS reduction from the baseline can be achieved without sacrificing other quality of results (QoRs) such as power and area. This methodology can be extended beyond FP-OPT as we demonstrated overall QoR enhancements using other Cerebrus applications such as the Congestion App.

MaxLinear 

Cadence Cerebrus solution utilizing the Cadence DDI (Digital Design Implementation) solutions of Genus/Innovus/Joules were used to save significant amounts of Dynamic power for a recent DSP based design in an advanced technology. In this presentation, we will discuss the AI/ML flow and results, and also any suggested improvements we feel might further improve it.

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

NVIDIA

Electronic Design Automation (EDA) faces increasing complexity due to the scale, intricacy, and knowledge-intensive nature of VLSI design. Engineers must meet stringent power, performance, and area (PPA) requirements, relying on domain-specific documentation, advanced foundry manuals, and specialized software tools for circuit design, logic synthesis, simulation, verification, and testing. As transistor counts and design complexity continue to rise, achieving high-quality circuits within tight PPA constraints becomes increasingly challenging. To address these challenges, we propose utilizing NVIDIA's Llama Nemotron model as a central reasoning and planning unit, complemented by Cadence’s software as agents, to automate and enhance the design process. This integration of NVIDIA’s AI-driven solutions with Cadence’s silicon-agent framework aims to streamline the electronic circuit design process, significantly improving efficiency and performance for future applications.

Marvell

Marvell provides semiconductor solutions across various market segments. To meet aggressive power and performance goals, we use Cerebrus to achieve competitive PPA targets on our latest generation 3nm design. In this session we will talk about use model, results, recipes, and drill down on specific features that we found very valuable.

Marvell

Analog circuit design requires decision making by the designers in terms of circuit topology, device choices and physical design implementation. Most of this acquired knowledge can be automatically transferred to new technology node by means of schematic migration and layout migration (for specific use cases only) hence improving productivity in the new technology node. 

In this quest we are partnered with Cadence to explore migration flows. Currently we are using schematic migration flow in production. Layout migration flow is under evaluation. It can be applied for certain design types and for others we are working with Cadence to enhance the tool based on our internal flow. 

In this presentation we will share our experience with both schematic migration and layout migration tools in Virtuoso.

Cadence

Get a sneak peek at upcoming developments in the Virtuoso Studio and Spectre platforms, including work done in support of Agentic AI. The enhanced technology encompasses all aspects of Custom IC design and will be relevant for both designers and layout engineers. In this session, we will be emphasizing what's new in our custom layout tools and design migration methods.

Medtronic

There is an increasing need for multi-modal, multi-sensor signal acquisition in implantable medical devices (IMDs) to improve the physiological state assessment and deliver lifesaving therapies. This requires design and implementation of a variety of analog/mixed-signal readout circuits that interface with a wide range of sensors. Coupled with the need for reduced power consumption, to increase the device longevity, necessitates the adoption of deep sub-micron processes to implement the analog/mixed-signal circuits. The well proximity effects, which are highly pronounced in these deep sub-micron processes, can significantly alter the performance of the precision circuits between schematic and post-layout extracted versions. This necessitates the need to implement a layout prototype that captures the accurate physical information, which the designers can then use to generate an extracted netlist and simulate to access the circuit performance, early in the design cycle. However, this pushes the layout resources into the critical path, which are already encumbered due to the stringent matching requirements posed by precision circuits and ever-increasing complexity of the design rule checks (DRCs) in sub-micron processes.

In this work, Cadence Animate Preview is explored as a productivity enhancement tool to create multiple layout prototypes that are compliant to pre-defined matching criteria. Layout candidates are generated through Animate Preview for two circuit topologies – 1) A current digital to analog converter (DAC) and 2) A reference buffer. Thanks to the DRC aware layout prototyping engine that powers Animate Preview, the generated layout prototypes (up to a maximum of 32) are DRC compliant and can be readily used by the designers to generate extracted netlists and simulate the designs with the well proximity effects and parasitics included. The candidate layouts can then be handed off to the layout engineers for further refinement. The introduction of Animate Preview in the design process reduces the time from schematic design to extracted simulations dramatically, thereby significantly enhancing the productivity and accelerating the design cycle.

Samsung Foundry

As semiconductor technology continues to evolve, migration has become an essential circuit design methodology that enables process node conversion, adaptation to changes in library, and the efficient reuse of IP. While schematic migration primarily involves logical conversion, layout migration is significantly more complex. It requires careful consideration of physical design constraints, routing strategies, and DRC/LVS verification. Due to these challenges, automation in layout migration is essential for improving efficiency and reducing TAT.

This paper presents an automated layout migration flow in Cadence Virtuoso, applied to a VCO design migrating from SF4 to SF2. The migration flow consists of several key steps. It begins with capturing the placement and routing topology of the source layout, which ensures that the essential layout topology is preserved. The next step is device mapping, which translates all devices correctly between process nodes. Following this, placement transformation applies reflection, scaling, and generation rules to maintain the design intent. Finally, routing leverages WSP-based auto-routing to enhance connectivity and reduce manual effort.

Through this methodology, the migrated layout might preserve circuit performance while achieving an improvement in TAT. The final LVS and DRC verification results confirm the accuracy of the migrated layout and ensure compliance with the new process constraints. By integrating automated placement and routing techniques, this methodology provides a practical and scalable solution for accelerating analog layout migration in advanced process nodes.

Intel

With semiconductor industry’s push to newer process nodes and shorter time to market, analog and custom IC layout creation has started to be the bottleneck as it has historically been a highly manual process. With analog IPs not undergoing major architectural changes across nodes, the ability to automatically recreate the designs based on the previous generations can reduce the costly iterations and help designs converge faster. The innovative approach of automatically inferring design intents from source layout and driving automated layout creation in target node has resulted in 50% improvement in layout productivity. 

The schematics on the target node are generated by mapping devices and parameters from the source schematic and optimizing them for the target node using customizable ML based engines. We used Virtuoso Schematic Migration Capabilities to get Our Target Schematics .

As a follow up of the paper we introduced the solution in 2024, this year we would like to present the results from successful usage of the tool in production. The time and effort savings even on the placement migration is significant as the flow honors the DRC and methodology requirements of the target node. Further we would discuss the expectations of routing migration and some early results.

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

Altera

To address the challenges of post-layout performance degradation in analog circuits, it is crucial to account for layout dependent effects in early stages. This paper explores how AI/ ML can be applied to consider the impact of parasitic effects in faster design closure, and a left shift strategy to achieve early-stage layout prototyping, floor planning.

This intuitive tool integrates seamlessly in the Cadence Analog Design Environment (ADE), with which designers will be able to synthesize high confidence first pass layout of Analog Mixed-Signal(AMS) circuits. The outcome is demonstrated by analyzing the synthesized layouts incorporating the crucial P&R constraints given by designer and use the AI/ML engine to improve the layout with each iteration. Adoption of the tool will demonstrate significantly reduced layout iteration time for parasitic critical analog circuits.

Intel

With the rapid advancement of technological innovations and applications, along with the growing sophistication of modern technologies, the demand for analog mixed-signal (AMS) design at advanced nodes is increasing. However, traditional AMS design implementation methods present significant challenges for design engineers, particularly due to increasing turnaround time (TAT) and the growing complexity of design rule checks (DRC) at these advanced nodes. A key challenge arises from the necessity of designing digital blocks within an analog environment to avoid cumbersome transitions between analog and digital workflows. At advanced technology nodes, these digital pockets introduce additional complexity due to factors such as different tap placement schemes, surrounding cell requirements, stringent pin connection routing rules, and an extensive set of design constraints. To address these challenges while maintaining design quality and development efficiency, Intel leverages the Innovus Implementation System, which integrates GigaPlace and NanoRoute engines within the Virtuoso Layout Suite. This system provides a fully automated placement and routing solution for the digital blocks, eliminating time-consuming manual transitions. GigaPlace supports a wide range of placement constraints, enabling automatic row generation, cell placement and, tap and filler cell insertion. Additionally, Cluster constraints based approach allows designers to define hierarchical groupings and placement of sub-blocks and standard cells, ensuring optimal proximity and adherence to design rules. NanoRoute engine’s seamless integration into Virtuoso environment for standard cell routing and block-level routing enhances routing efficiency. By incorporating the Innovus based tools into the AMS design workflow at advanced nodes, we aim to overcome placement and routing challenges and improve layout design productivity.

Texas Instruments / Cadence

The Midas Safety Report Creator is a Cadence application that, leveraging an input database, allows system integrators to customize production functional safety analysis and to generate reports.

The input database is created by the Midas Safety Database Manager utility and stores the set-of supported variables and actions the system integrators can configure with the reference of a production safety analysis, as for example: changing the device package between the ones pre-configured and refine the safety scope for a given application. 

Both applications, Midas Safety Database Manager and Report Creator are now part of the Midas Safety Platform solution. 

By leveraging the Midas USF backend technology, the Midas Safety Report Creator application can recompute ‘on the fly’ the safety metrics so that reports can be generated to be used in integrator’s safety lifecycles, including evidences to be provided to assessors. 

From the architectural point of view the Midas Safety Report Creator is organized in three layers: a front end – that collects to customizations for the end-users, an interface layer, which summarizes the configuration into a JSON file, and a backend, which parses the JSON file and performs the requested actions. 

The solution represents a first industry that allows propagating safety engineering information into the automotive and industrial supply chains, allowing integrator’s customizations without potentially any specific support engagement. Protection of the confidential product information is guaranteed by the encryption applied to the shared database.

The concept of the solution and the collaboration between Cadence and Texas instruments have been preliminary introduced at the 2022 CDNLive EMEA, with a presentation having the tile 'Functional Safety Analysis: deal with integrators customizations'. Following that event, in October 2023 – the first production version of the Midas Safety Report Creator has been released and let available to selected Texas Instruments customers. Then Midas 23.09 has been the first production release to integrate both the Midas Safety Database Manager and the Report Creator. In the meanwhile, the solution has been further improved and tailored to the Texas Instruments needs and requests coming from the end-users.

In this presentation we summarize the solution features, the status of adoption for Texas Instruments customers, and challenges ahead.

GlobalFoundries

GlobalFoundries, a leading semiconductor manufacturer, offers automotive design enablement through differentiated process node offerings including FDX and FinFETtechnologies. Automotive design presents stringent reliability requirements for device aging margins. These margins are key for design reliability but also influencing Power Performance Area (PPA) design metrics.

Current safe but pessimistic design methodologies use timing views that are characterized at the end-of-life aging behavior across the entire design regardless of the actual instance specific aging stress. Cadence novel Liberate/Tempus Advanced Aging flow implements instance and activity-specific aging degradation and therefore promises increased accuracy and improved PPA.

This presentation details the Advanced Aging setup within a Liberate based characterization flow and how to use advanced aging timing libraries within digital static timing analysis using Tempus. We introduce a methodology for correlating the current with theadvanced aging methodology at the device degradation and STA level. The confirmation of correlation between the current and the advanced approach enables the productization of this aging characterization as a next step.

GlobalFoundries

Cycuity 

Verifying the effectiveness of security functionality and measuring it through coverage across the pre-silicon development cycle is critical to ensuring that hardware designs remain resilient against potential threats. Without a systematic approach, organizations risk leaving vulnerabilities unaddressed, which can lead to significant financial, reputational, and operational losses once an IP, IC, or system reaches the market. 

By quantifying the coverage of security components, teams can identify and understand security gaps early in the design phase which enables them to implement mitigations efficiently and cost-effectively. This proactive approach not only ensures compliance with industry standards but also boosts customer confidence in the final product.

In this work, we will demonstrate the utilization and seamless integration of Cycuity’s Radix products into the Cadence verification environment to generate security coverage data.  By leveraging Radix, we are able to create a dedicated security coverage database which is then visualized, analyzed, and managed within Cadence platforms such as vManager or IMC, ensuring comprehensive and efficient security coverage management. 

This paper also introduces a methodology to develop and measure robust security requirements by threat modeling early in the design process. It will identify and prioritize risks, verify the effectiveness of security features, and effectively incorporate approaches such as MITRE’s Common Weakness Enumeration (CWE).  Building on these foundational steps, it will also emphasize the importance of assessing how much of design’s intended security measures have been tested and exercised during the verification process. Doing so can ensure products are equipped to withstand evolving threats while maintaining a strong competitive edge in today’s security-conscious market. 

The resulting coverage reports are valuable for demonstrating evidence of security to external stakeholders, including customers, regulators, and auditors. They demonstrate compliance and accountability, serving as concrete evidence of an organization's commitment to strong security practices. For example, adherence to industry standards such as ISO 21434 or NIST frameworks becomes far more credible when supported by detailed, actionable reports that align with required security guidelines.

Cadence

Integrating advanced digital signal processing (DSP) technologies in vehicles is revolutionizing the in-cabin experience, safety, and communication systems. This presentation explores the application of Cadence Tensilica Audio, Video DSP, and AI cores in modern vehicles, focusing on enhancing safety, comfort, and immersive audio experiences. 

Key applications include child presence detection, event detection for safety and intrusion alerts, and leveraging radar and acoustic sensors to identify potential hazards or unauthorized access. Immersive audio systems create a personalized sound environment, while 3D depth sensors such as time-of-flight (ToF) cameras coupled with audio add safety for advanced driver assistance systems. Outside sound detection enables vehicles to identify and respond to external auditory cues, such as emergency sirens or pedestrian presence, and radar sensors provide safety functions to both passengers and vulnerable road users (VRUs). Discover how DSP technology powers automotive safety and connectivity advancements and enables such applications.

Texas Instruments

With extensive heterogenous IP integration and adoption of advanced FinFET technologies in recent automotive system on chip (SoC) designs together with accelerated volume ramp goals, traditional test and diagnostic methods are no longer sufficient to meet cost-effective quality and near-zero DPPM (defective parts per million) requirements expected by the automotive markets.

The organization of the paper is as follows.  First, we shall introduce challenges with volume diagnostics and failure analysis integration for yield learning. Then, we shall present case-studies on recent enhancements in Modus diagnostics tool capabilities for cycle-time reduction. Subsequently, we shall present innovative scheduling and slice-based diagnostics flow for accelerated yield improvement. Finally, we shall conclude with deployment results from multiple automotive and industrial SOCs.

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

Cadence

The talk will start with ISO26262 compliance market opportunities and challenges for Cadence FuSa services team, SVG Tools team, and IP team. All those groups have different business goals but need each other to collaborate on those FuSa businesses. After the introduction, the focus will be directed toward systematic (process) and RnD issues we face while working on ISO26262 compliance for our IPs. The Prove of Concept automated FuSa flow will be described to show how we got ISO26262 compliance work products faster thanks to the implemented automation in the flow and how it can fit to leading functional safety industry standards and the current Cadence overall Functional Safety offering. The conclusion will summarize the next steps and innovation ideas.

Texas Instruments

The Cadence Midas Unified Safety Format (USF) enables functional safety analysis authoring according to ISO26262 and IEC61508 standards, including support for basic failure rate computation, and reporting. Midas USF is available as embedded into the Cadence Genus synthesis solution and it is also integrated as the backend of the Midas application.

The command set provided by the Midas USF is supposed to be generic to be used for different use cases, functional safety lifecycles and methodologies, but one of its goals is to also enable end-users to develop their own custom automations as for example by interactively query the safety information in the USF memory. In this way the end-user can “stretch” USF to easily adapt to specific needs and to enable automations not directly available into the Midas Safety Platform.

Here we present the framework developed by Texas Instruments on top of Midas USF, that fully integrates the company functional safety methodology, that includes a planner worksheet (FMA) and the usage of the elementary subparts (as for ISO26262-11 2nd edition). The framework is also able to collect the design information used in the safety analysis (detailed FMEDA).

The presented solution results to be an automated and robust framework to take multiple IP FMAs as input and to generate the production SoC FMEDA with no manual intervention in the flow, including quality checks at each key point to cross-check for any potential issues or inconsistencies. The developed framework is robust enough to be used for any SoCs across the Texas Instruments Business Units.

Cadence

Large Language Models (LLMs) data sets are growing at an exponential rate and current CPUs and GPUs performance is often limited by the available memory bandwidth. Because of this memory wall, High Bandwidth Memory (HBM) is becoming the memory of choice for generative AI training due to its superior bandwidth, capacity, and memory efficiency.  HBM has been a rapidly evolving memory standard quickly moving from HBM2 to HBM3 and now to the highly anticipated HBM4.  The implementation of HBM memory, due to its wide data path (1024 bits), can be challenging to system designers since some type of interposer technology is required. This presentation will discuss how Cadence HBM memory IP subsystems provide the highest performance available and along with the system reference design and tools to easy HBM implementation for our customers. 

OpenEye / Cadence

The discovery of new human medications has never been more important in preserving and extending human health and life. This has been amply demonstrated by the impact of vaccines and medications on COVID infections, and the sometimes astounding effects of GLP-1 agonists (such as Ozempic) on a huge range of human diseases, including diabetes and obesity. Despite these high-profile successes modern drug discovery faces significant challenges; getting new medications to patients, whether small molecules, biologics, macrocycles, or degraders, has never been more time-consuming and expensive, usually requiring more than 12 years and $2B. It is also very risky, with nine out ten drugs failing in clinical trials. At Cadence Molecular Sciences we are combining deep experience in developing software to improve drug design with Cadence’s deep technical expertise and broad industry connections to accelerate and de-risk designing new human medications. We harness the power of cloud-scale computing, GPU acceleration, and AI to search through enormous molecular spaces to find the best hit molecules for the early stages of a discovery project. We use efficient and accurate molecular simulations to optimize those hit molecules into drugs and then predict the most effective pill form to deliver those drugs to patients. Under Cadence leadership and through customer collaborations, we are expanding our tools from our strength in small-molecule drug discovery toward cryptic pocket identification, cryogenic electron microscopy, biologic therapeutics, formulations, and generative AI via integration of NVIDIA’s BioNeMo. Together, these exciting advances enable pharmaceutical and biotech companies to discover and develop the therapeutics of the future.

Cadence

Today PHY IP designers using Cadence tools (mainly Spectre simulator) are not able to perform Serial Link Interface analysis in their native environment: Virtuoso. This is a competitive disadvantage versus competitor tools like Synopsys Hspice PrimeSim. A serial link channel simulation enables high capacity (ex. million bit) simulations, BER analysis (bathtub curve generation) and IBIS-AMI model support for real-time adaptive equalization. Cadence´s SystemSI has the industry-leading channel simulator and it can be integrated into the Virtuoso / ADE environment. In this work we demonstrate a channel simulation overview, how it works today in SystemSI and how it could be integrated into Virtuoso´s environment, the implementation itself (including IBIS-AMI modeling for channel equalization) and simulation results.

Cadence

The complexity of modern systems requires groundbreaking approaches to design and verification. Traditional approaches to multiphysics analysis fail to address these complexities, particularly early in the design process when they can have the greatest impact. Learn how in-design analysis enabled by accelerated computing, high-fidelity simulation, and ultimately physical AI is changing all this, with early-stage detection of thermal instabilities, stress/warpage, and power inefficiencies. Discover how our innovative approach ensures faster design cycles, enhanced accuracy, and unparalleled insights—turning system design challenges into opportunities for competitive advantage. 

Cadence

As SoC design paradigms evolve, comprehensive verification solutions are essential to prevent costly tape-out failures. Cadence Helium, an advanced EDA tool featuring both a Helium Virtual Platform and a Helium Hybrid Platform, enables early software development for SoCs and ensuring thorough verification coverage. With the novel ARM-on-ARM feature in the Helium Virtual Platform, the efficiency of software development in the virtual platform is almost the same as in the native platform.

Cadence Helium is a game-changer for Vehicle SoC manufacturers and companies needing robust architecture design and pre-silicon software development. Helium platforms facilitate early software development and mitigate costly tape-out failures. It also integrates with Palladium and Protium systems, making it particularly beneficial for AI companies using advanced fabrication technologies like TSMC N2/N3 nodes. Its effectiveness is proven by widespread adoption among major IC design companies worldwide.

Join us for an insightful session, don’t miss the opportunity to explore the future of efficient SoC design and Verification with Cadence Helium Virtual and Hybrid Platforms!

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

Cadence

Cadence OnCloud revolutionizes EDA and system design workflows by offering a suite of value-add services that enhance productivity, cost efficiency, and design quality. This presentation will explore how Cadence OnCloud integrates automated EDA flows, seamless job orchestration, and efficient data synchronization to create a scalable and secure semiconductor chip and systems design environment.

The True Hybrid Cloud setup ensures seamless job orchestration between on-premises compute and Cadence Managed Cloud, optimizing compute resources and minimizing data movement. In addition, Cadence OnCloud provides comprehensive and fully automated EDA flows in the cloud, including synthesis, P&R, full chip timing, IR drop analysis, and physical verification, improving your design TATs.

IBM Research 

Analog In-Memory Computing (AIMC) is a promising option for hardware acceleration of AI. However, AIMC comes with various device and circuit-level non-idealities that can impact overall DNN accuracy. Design simulation and analysis are crucial to understand compute accuracies of AIMC designs and identify optimization opportunities. Hundreds of simulations are required to cover various operating conditions and explore the design parameter space.

Cloud bursting EDA workloads allows for significant job parallelization and job throughput for Mixed-Signal/Analog transient circuit simulations using Cadence Spectre. Utilizing the IBM Cloud for job distribution facilitates the generation and analysis of large amount of simulation data that is crucial to the design process of AI accelerators.

Amazon Web Services

Amazon Forecast is a fully managed service that uses advanced statistical and machine learning algorithms to deliver highly accurate time-series forecasts. For example, you can use Forecast to analyze your past orchestration (such as LSF or Slurm) account data, which contains time-series resource usage information. Forecast can then train a predictive model on this historical data to forecast your future resource needs.

Avicena Tech

Avicena Tech, a pioneering startup in low-power IO connectivity, has successfully leveraged Cadence's full-flow toolset on Managed Cloud services to enhance its high-performance computing capabilities. This paper explores transitioning from on-premises infrastructure to a scalable, flexible, and cost-efficient cloud solution. Key benefits include improved design flow efficiency, rapid support, and seamless scalability, which have significantly boosted productivity and innovation at Avicena Tech. The integration of Cadence tools has streamlined their analog and digital design processes, leading to faster turnaround times and higher quality outcomes, fostering a culture of innovation performance, reducing turnaround time, and enhancing team collaboration. 

Presentation Takeaways:  The presentation will highlight how Avicena Tech has significantly enhanced its design flow efficiency by leveraging Cadence OnCloud Managed Cloud Service. It will discuss the scalable and flexible cloud solutions implemented, allowing seamless upgrades and adjustments during peak times. Additionally, the presentation will cover the cost-effective IT management strategies adopted, leading to substantial savings. Finally, it will emphasize how these improvements have boosted productivity and fostered a culture of innovation at Avicena Tech 

IBM

What would you do if you were told that your Cadence workloads were running slowly in the cloud?  You know the products and services they are using are proven in many other clients around the world, so what just what is going on here?  You assemble a cross-IBM team of experts in cloud, storage, performance, and Cadence applications and apply a rigorous engineering methodology of hypothesis, experimentation, evaluation and iteration.  You make design changes to improve resilience and deliver a set of optimizations that not only show significantly better performance, but also help pave the way for future optimizations for other Cadence users running within IBM Cloud.

This is that team’s story…

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

Google

Growing demands of modern chip design requires a paradigm shift in EDA. Google Cloud Platform (GCP)’s High Performance Computing (HPC) capabilities provide scalable and efficient solutions to meet the demanding requirements of EDA workloads. Drawing on insights and best practices from Alphabet's internal deployment of Cadence tools, we will demonstrate how Google Cloud services like Google Kubernetes Engine (GKE) and Cloud Batch can handle the dynamic compute demands of Cadence tools, while Google Cloud Storage (GCS) and BigQuery streamline data management to optimize analysis for Cadence projects. Furthermore, we will explore how runtime optimizations and fine-grained access control in GCP can be crucial for achieving significant improvements in chip design efficiency.

Akeana

Akeana, a startup developing high-performance RISC-V processor IP, faced time-to-market challenges in bringing a broad IP portfolio with highly configurable designs to market. To optimize development cycles and address the complexity of HW/SW co-verification, Akeana utilized Cadence’s Palladium solution on cloud to accelerate microcontrollers, Big-Little application cores, high performance data center cores, as well as multi-threaded cores for networking and other high throughput applications. This presentation will describe how Palladium Cloud is used to emulate various RISC-V workloads and interface protocols so DV team can quickly identify and resolve system-level and performance bugs that can only be traced at system-level and with real-world workloads. It will also describe the compute infrastructure related to Palladium Cloud and how Akeana is able to easily leverage this subscription service without having to build its own data center to host and operate emulators and related compute.  

AMD

Analog and RF design simulation and verification become increasingly challenging at 7nm and below. The severity of impacts of inter-connect RC on circuit performance, reliability and power consumption grows. To capture these effects, large scale parasitic RC components are included in post-layout simulations, which push the limits of simulation speed and capacity. Especially, RF simulations at post-layout stage require enormous amount of memory. Another example would be top level analog IP verification at the post-layout stage, which usually takes exceedingly long simulation time. To this end, massive parallel simulators such as Spectre X are commonly used to improve simulation performance. However, the resource required by parallel computations is usually constrained by the number of CPU cores and memory that each user can access on the server farm. The newly introduced Spectre XDP technology addresses these constraints by distributing simulations across multiple machines and cores and provides significant performance and capacity improvements for large-scale circuit simulations.

This paper first overviews the challenges in AMD analog and RF design and verification at advance node processes. Next, we will show the performance improvement using the Spectre X XDP technology, particularly in RF analysis on high frequency voltage control oscillators. Furthermore, we will discuss how we optimize the Spectre X XDP set up for analog top-level designs such as PLL post-layout simulation from both simulation throughput and hardware configuration perspectives. Future enhancement requests will be presented at the end.

Cadence

Get a sneak peek at upcoming developments in the Virtuoso Studio and Spectre platforms, including work done in support of Agentic AI. The enhanced technology encompasses all aspects of Custom IC design and will be relevant for both designers and layout engineers. In this session, we will be emphasizing updates to our Spectre Simulation Platform and new analysis methods available to Virtuoso ADE users.

Texas Intruments

Although calcVal is “only” another Skill function, the complexity often makes it hard to deal with it. With enhanced setup help in expression builder and especially through calcVal wizard, the setup became way easier. With the lint checker it can be easily ensured, that the expressions are still valid after maestro state changes. 

Besides the regular trim setup, calcVal can also help you to improve your simulation throughput. There are obvious ways to that, for example referencing a trim value from an existing history. But there is also hidden potential, like carrying over the dc solution for your transient analysis from one history to the next. With calcVal it becomes easy to reference the dc solution (spectre.ic file) from the right sample of the previous run. 

In the presentation we will show, how we use calcVal in our environment and show how we gain efficiency in our workflows using calcVal.

Infineon

Infineon's analog design team considers analyzing device manufacturing variability a key part of its functional verification flow for comparators in PMU designs. This analysis allows the team to center the design, improving yield and/or reliability. Traditionally, this kind of verification used Monte Carlo-based simulations to generate the statistical data and variations. However, as the number of process corners, voltage, and temperature combinations increase and as yield targets become more stringent, comprehensive design exploration across these combinations become prohibitively expensive. Infineon recently benchmarked the AI-enhanced Cadence Spectre FMC Analysis's smart corners technology to bring variation analysis into reality. Spectre FMC Analysis dramatically reduced the number of Monte Carlo simulations while retaining the necessary accuracy. We summarize the results of the benchmark and illustrate the improved turnaround times to help us meet tape out schedules.

InPlay 

In recent years, the complexity and performance demands of chip design have increased significantly, leading to higher power dissipation in VLSI chips. As a result, it is crucial to estimate power dissipation as early as possible in the design process to optimize designs and reduce power consumption. Additionally, adhering to cooling and packaging constraints is essential in modern design environments.

Early-stage power estimation plays a key role in optimizing designs and addressing power-related challenges. While post-route power measurements provide highly accurate results, early-stage power estimation enables the proactive implementation of low-power techniques, allowing for the early resolution of power issues. The feedback loop from late-stage power measurements to the RTL design phase helps designers promptly identify violations and apply appropriate low-power strategies. This iterative approach improves design robustness while ensuring compliance with power constraints and performance goals.

In addition, this type of analysis allows exploration of changes in the RTL design with a greatly reduced runtime, as RTL designers do not have to wait for the synthesis, place and route, and signoff processes. 

This study uses Joules from Cadence, a powerful tool for RTL power estimation power data analysis. The testcase is an automotive SoC in FDSOI technology. As expected, a discrepancy in power values between the RTL and P&R stages is observed, since the RTL stage lacks detailed information about wires and interconnects. The findings indicate that RTL power estimates are within 10% of signoff power values, demonstrating the effectiveness of early-stage power estimation.

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

NASA Jet Propulsion Laboratory 

NASA is exploring the Mars Science Helicopter (MSH) mission concept which is a large helicopter for exploring Mars’ polar regions which show evidence of harboring subsurface ice. While the presence of this ice is not disputed, its origins and the nature of its emplacement remain the subject of debate in planetary science. Several models of massive emplacement and growth via vapor deposition have been proposed. As part of the MSH concept, JPL is proposing to carry a custom chip-based ground penetrating radar (GPR) developed specifically to investigate sub-surface ice and the observables that could identify ice emplacement mechanisms. This talk will discuss the design of the radar chipset with spectre-based simulation methodologies combined with physical modeling of Mars’ subsurface, that are together used to optimize the radar’s waveforms, parameters, and architecture and make predictions about the obtainable sensitivity, resolution and penetration once at Mars’ surface.

Texas Instruments

With many of the PDK lifetime reliability factors now covered with asserts, getting better use out of assertions is critical. Some internal tools and scripts have been developed to help process the assertion violations generated, but what can we do to ensure assertion checks represent our parts' usage? 

Spectre assertion checks during the entire transient simulation can slow down the simulation.  The fast startup or fast loading techniques enabled in the stimulus have drastically improved the simulation performance.  However, they create false assertion violations due to fast transitions. Some simulations may need reliability assertions to be ignored during startup for the lifetime FIT calculation. Multiple assertions during transient analyses can cause simulations to slow down due to the assertions exported in the log. 

In some cases, you may have a specific window (or windows) of time you would like to do the checking. Assert windows allow the user to control what time frames asserts are active, allowing better assert checks, if used properly. 

Spectre assertion check_windows using a text file: the format is point pairs separated by spaces where each pair defines the start and stop of a time window. However, the “start” and “stop” times are fixed in check_windows=[‘start’ ‘stop’]. For corner regressions, the desired start and stop time can change from corner to corner. Fixed timing makes it difficult for the testbench’s portability and reusability.

In this paper, we presented two new VPI functions developed in Xcelium, that you can control either the domain of the assertion state or the domain of assertion severity. These VPI functions are currently supported in System Verilog and Verilog digital blocks only. A case study of lifetime tests (HTOL/BHAST) shows the use of assert windows reduced the runtime drastically while keeping the same accuracy. 

Takeaway: In summary, Cadence’s new VPI functions make it possible to align the assertion checks with the real designs’ usage model. This greatly improves mixed-signal verification’s productivity by:1. Reduce the great number of false assertion warnings; 2. Reduce the runtime to make the simulation more efficient with good accuracy.

MediaTek

High Performance CPU cores are growing every year to improve IPC and meet increasing compute needs of modern applications. Pushing Fmax on these cores for flagship smartphones is critical as it helps with faster app launch times, smoother multitasking, and overall better responsiveness, enhancing the user experience. Flat implementation of these multimillion transistor CPU poses high run time and memory footprint challenges.  This further limit number of DoEs during execution cycle to achieve best PPA.

Divide & conquer using hierarchical implementation is a feasible solution to above mentioned challenges and improve execution TAT.  Using Smart Hierarchical Partitioning technique, we were able to partition the CPU at optimal boundaries. All the top level macro location, PDN & clock tap points was pushed into the partitions to give optimal start point for block level implementation.  

From here all the partitions were individually implemented using PODv2->COD->ROD which is 1.5X faster than traditional implementation flow. We utilized advanced wire delay optimization techniques using optimal via pillars and signal NRDs to extract every ps from net delays. 

IO budgets derived through Innovus Smart Hierarchical flow can be inaccurate due to different module placement, latencies at block level v/s top. These inaccuracies can lead to IO timing closure challenges when blocks are merged at TOP level, and we may see lot of interface paths limiting Fmax. 

Context based optimization provides solution to this. CPU is first reconstructed by assembling design with full block DBs at postroute. ’Context’ captures actual data path delays and clock arrivals on IO paths as seen from Top level when pushed down into blocks, this removes the IO timing gap seen between blocks and Top. We were also able to pull in context based optimization at preroute stags to give Innovus more flexibility & opportunity to improve PPA. 

Using smart hierarchical partitioning and later context based optimization, we were able to reduce the overall TAT by 3X compared to Flat implementation. This faster TAT helped to improve our recipe including wire optimization techniques for best PPA. Using context opt, we were able to clean up most of the interface timing outliers and achieving extra +80MHz out of Innovus and ~30% better TNS ensuring smooth last mile closure.

Samsung Electronics

As the power efficiency of semiconductors becomes increasingly important, the demands of device scaling is very powerful. However, due to physical constraints caused by device scaling, the channel width of extreme high density (xHD) cell decreases, resulting in a decrease in cell speed and drivability. This problem not only weakens the maximum chip performance but also reduces power efficiency. In this paper, we introduce a design methodology using hyper cell that merges adjacent channels to solve the problem of speed degradation due to device scaling. The hyper cell has place and route (P&R) constraints to prevent a process risk caused by a jog paatern near the merged channel. We introduce P&R strategies to minimize the physical overheads from the P&R constraints and maximize the performance gain of hyper cells.

NVIDIA

As design size increases, reliable Power Distribution Networks (PDN) become ever more critical. Any voltage drop at the transistors will have a dramatic impact on circuit performance. Nvidia have developed a high speed PG mesh creation flow based on Innovus Flash PG Synthesis, using the new PG Structure Description Language (PSDL). Join this session to gain an insight into how Nvidia can rapidly insert PDN into many blocks improving reliability and efficiency.

Arm

Arm has adopted the new Innovus FlashPG Synthesis capability in it's power distribution network implementation flow, reducing the run time by over an order of magnitude while optimizing the power distribution and enabling the design of complex power grid network. Flash PG is based on a high level language called PG Structure Description Language (PSDL), which is used to specify the PG grid parameters. With Arm's ability to identify different region types in the block and map predefined PSDL power grid structures to each type, Arm can efficiently implement a power delivery network on unique blocks from one set of predefined PSDL power grid structures. Join this session to understand how Arm are using Flash PG to automate Power Distribution Network implementation.

Google

In Google, the synthesis and PnR steps are done by the physical design team. Starting a new project, there was a need to receive early feedback on RTL metrics concerning power performance, area and congestion (PPAC).

Typically, it is done by multiple iterations with the physical design team. However, when working on a brand new IP, especially one with high frequency requirements, the physical design team is required for a significant bring-up and a lot of collaterals in order to start producing a viable meaningful picture of the timing, area and congestion. Instead, it was straightforward to use RTL studies on the FE side to quickly and clearly make design related decisions on functionality and hierarchy, as well as good timing predictability. All was done with multiple and fast iterations. 

The tool ramp up was done quickly. We were also able to use the floorplan prediction features and to predict timing issues related to physical aspects, when the real floorplan wasn’t available yet.

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

Cadence

Logical equivalence checking (LEC) is essential for efficient RTL-level functional verification during design implementation, ensuring later design stages are logically equivalent. However, increasing SoC complexity and the rise of multifaceted functional ECOs have created new challenges, particularly for inexperienced designers. In order to significantly speed up and simplify EC and improve the entire functional ECO process, design teams require a new approach to both flows.  This R&D presentation will introduce Conformal AI Studio - a new suite of logical equivalence checking, automated functional ECOs generation, and low-power static signoff products from Cadence. 

With artificial intelligence and machine learning (AI/ML) capabilities, Conformal AI Studio directly addresses the increasing productivity demands of modern SoC teams. This is achieved through core engine speedups, new algorithm innovations, and simplified setups and AI-enabled flows for LEC and ECO solutions. New ML-driven abort resolution tackles the most complex LEC problem advanced users face today. Conformal AI Studio delivers an order of magnitude higher designer productivity and smaller and faster ECOs and enables optimal full-flow power, performance, and area (PPA) by supporting the most advanced implementation tool optimizations. Come learn about the next generation of Conformal!

Cadence

With chip designs getting larger and more complex, enabled by the latest advanced process nodes, the Cadence Digital Implementation and Signoff flow is always innovating to address future challenges. The new 25.1 product release is underway, which will deliver many new technologies such as Arm and GPU compute support, AI driven design and formal verification, and Large Language Model (LLM) assistants. Join this session for an overview of current and future Digital Implementation and Signoff development.

Qualcomm

In-design convergence of Timing, Power, Physical Verification, IR-signoff are key components to meet the time to market (TTM) for silicon designs. Existing methodologies for IR-prevention and repair consist of local PG grid beef-up, over-designing the global grid, cell spreading, output load splitting. All the techniques are manual and potentially impact the performance. IR-prevention has become a complex problem which requires fully automated method that effectively balances performance, grid resources, and manufacturing costs. 

In this paper, we will discuss newly developed solution that separates per instance IR-drop into (i) lower layer drop due to simultaneous switching of aggressors (ii) Mid-upper layer drop due to grid weaknesses in power-delivery. This paper also discusses grid-repair methodology tuning required for switch domain violations. 

For CPU blocks, there are well accepted time-based vector payloads (such as max-power, dhrystone, di_dt, etc.) for power optimizations and IR-profiling. With the proposed methodology, we observed 80.028% less IR violations in signoff analysis without significant impact on power, performance, area, track-utilization, and overall runtime.

Samsung

Microchip

With technology node scaling, and the increased design complexity of integrated circuits (ICs) grows, achieving defect-free chips is of prime importance. Multibit cells, such as flip-flops, and standard cells with small sizing are prone to defects. The smaller the technology nodes, the larger the chances of undetected faults and test escapes. This paper tries to overcome these challenges and aims to propose a multi-layered ATPG methodology which aims to improve the quality of IC design methodology by integrating Cell-Aware Test (CAT) ATPG, Timing-Driven ATPG, and Total Critical Area (TCA)-weighted ATPG (AFG). Unique fault universes are targeted by this comprehensive approach, enhancing fault detection and improving test coverage substantially. Cell-Aware ATPG addresses cell-internal defects, such as transistor opens and shorts, achieving a sixfold increase in faults detected compared to traditional methods and a ~ 3.31% improvement in test coverage when used as a top-off on traditional stuck at fault detection and ~ 9.6% improvement in the dynamic fault testing. TAA focuses on transition delay faults (TDFs) in critical paths with minimal positive slack, detecting timing issues caused by process variations or aging. While TAA does not significantly improve coverage, it strengthens the robustness of fault detection in timing-critical paths, improving circuit reliability over time. Complementing these, TCA-weighted ATPG identifies intercell defects like bridging faults by focusing on regions with high defect probabilities, increasing fault detection by 2.6x over conventional approaches and boosting coverage by an additional ~ 0.35% in stuck at and ~ 0.89% in TDF. This comprehensive framework ensures better stuck-at and TDF coverage, reducing test escapes. Experimental results confirm its efficacy, enabling reliable, high-performance IC production while addressing the challenges of modern technology nodes.

Samsung

This paper focuses on characterization prediction, a technique that utilizes machine learning modeling to estimate specific corner values using library data from different corners without real simulation. In more detail, the method allows for the input of more than two Anchor PVT sets, from which it extracts corresponding liberty files, referred to as target PVT values.". This method is particularly beneficial in the advanced nodes, where there is an increased demand for diverse characterization conditions and the need for validation in ultra-low and high voltage domains to ensure high-quality libraries. This method significantly reduces runtime by using  ML-based modeling prediction, maintaining the same resource cost and thus shortening the turnaround time.  Despite this resource efficiency, it consistently delivers a high accuracy rate of 99% across various data types within reasonable tolerances.

TSMC

In the rapidly evolving semiconductor industry, efficient and accurate physical verification is crucial for reducing time-to-market and ensuring design integrity. In this presentation TSMC explores the integration of Virtuoso InDesign Physical Verification with Pegasus, highlighting its impact on advanced methodologies and design challenges. TSMC delves into the benefits of in-design signoff verification at the early stages of layout development, emphasizing real-time feedback and native sign-off verification.

Key topics include the advanced methodologies flow, challenges during layout development on advanced process nodes, and the productivity boost achieved through iPegasus Verification System for Virtuoso Studio, which includes DRC, FILL, and LVS flows enabled for in-design. We also discuss the seamless integration of Pegasus, which enables running foundry-certified signoff decks within Virtuoso, supporting multiple TSMC nodes where nodes above 28nm are supported with PVS and nodes 28nm and below use Pegasus decks certified by the foundry.

The presentation showcases significant runtime improvements, accelerating signoff verification by 2X, and the intuitive GUI that facilitates easier access and debugging of signoff DRC violations. Attendees will gain insights into how iPegasus for Virtuoso Studio reduces turnaround time, offers robust infrastructure, and provides accuracy through foundry certification.

Additionally, we will explore how in-design signoff verification on advanced process nodes like 2nm and above provides signoff-quality on-demand DRC verification and fill insertion on either the entire layout or partial layout depending on layer visibility or changed area. This approach is essential for catching DRC violations and predicting metal fill impact early in the design process, leading to faster full flow TAT and shortened design cycle time, thereby boosting productivity.

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

Renesas

Renesas has successfully adopted Pegasus DRC on advanced node process SoC. The team faced numerous challenges, including the management of CPUs and memory. By deploying the Pegasus Physical Verification solution and leveraging Pegasus in-design flows integrated in Innovus, the team achieved enhanced productivity and predictability for DRC closure. Strong collaboration between the Pegasus teams and the designers of the Renesas EDA/Design team resulted in the successful use of Pegasus for DRC and FILL.

MediaTek

Power integrity in high-performance computing systems is crucial for ensuring reliable and efficient operation. With each generation, high-performance CPU cores are significantly increasing in area and power to meet compute needs. Power integrity has become a critical factor in CPU silicon performance, as CPUs are starting to throttle before achieving the STA frequency due to power budgets and thermal limitations. General-purpose CPUs used in various product segments often face coverage issues, making it challenging to sign off on power integrity with a limited number of vectors. Therefore, a global solution is needed to ensure robust electrical performance and reliability.

Global PGFill provides reinforcement to the existing Power Delivery Network (PDN), improving PDN resistance, reducing voltage drops, and minimizing electromagnetic interference.

In this paper, we discuss how we utilized opportunistic track-based PGFill using Cadence Pegasus and optimally integrated it with the existing PDN to enhance power integrity while addressing challenges such as runtime and timing degradation. We propose our custom solution by optimally controlling STAMP lengths in Pegasus, adding additional PG VIAs, and improving the overall effective resistance of the design. We also address key challenges, such as timing degradation caused by PGFill, and how our custom solution helped to minimize these issues. Additionally, we highlight our close collaboration with Cadence PE/R&D to enhance Pegasus features, including absolute stamp length, critical net protection for clock/data nets to avoid timing degradation, and enhanced incremental PGFill.

Using the proposed custom solution, we achieved an improvement of approximately 20% in overall PDN resistance and 68% cleanup in overall dynamic IR violations, resulting in a more robust design. All of this was achieved without introducing any additional DRC violations.

Raytheon Technologies 

Last year we achieved a successful tapeout using the Cadence Stratus HLS tool. However, our design started as a MATLAB model which had to be manually rewritten as SystemC before Stratus could turn it into hardware.

This paper recounts our experience *this* year using a new automated MATLAB to Stratus flow. This flow took our MATLAB M-code files, turned them into SystemC, and ran them through Stratus logic synthesis. We also used Cadence Cerebrus to define an exploration space and let machine learning find the very best area and power. This flow produced hardware that exceeded last year’s PPA results for the same design.

Stratus HLS quickly generates functional RTL much faster than traditional hand RTL. HLS designs are untimed, algorithmic SystemC modules that are easier to write without the burden of cycle-accurate implementation. While your first PPA results from HLS may be worse than your target, with Stratus you can use different synthesis directives to quickly produce new RTL that usually meets and exceeds those targets.  This all worked great last year, but our design actually began as a MATLAB model which we had to rewrite in SystemC by hand before we could run Stratus. This year, thankfully, we used a new automated MATLAB-Stratus flow that saved having to rewrite anything.

This flow seamlessly marries MATLAB algorithm development with Stratus high-level synthesis, simulation and exploration. We verified this flow provides consistently good PPA superior to our previous hand-coded, hand-optimized HLS result.  Just simulate your MATLAB M-code as normal, then use the HDL Coder’s Workflow Advisor where all steps of the flow are configured and run, including all the downstream tools that Stratus supports like Xcelium/Jasper verification, Conformal equivalence, Joules power estimation, Genus logic synthesis and more.

At this point you can add synthesis configurations to explore different Stratus RTL results, or do what we did and automate that process as well using the Cadence Cerebrus tool.  With Cerebrus you can define an exploration space and cost function and use AI to run all possible combinations and find the very best result. Early Cerebrus runs have shown upwards of 17% area and power improvement. 

With this new and effective flow, SystemC and RTL are no longer a barrier for our MATLAB-oriented engineers to adopt HLS, and it enables finding architectures they never would have had time to write by hand.

STMicroelectronics

Traditionally, transitioning from a MATLAB algorithm to synthesizable RTL involved a manual and heavy conversion process, leading to delays in obtaining accurate power, performance, and area (PPA) data. This presentation highlights the successful implementation of an automated flow encompassing MATLAB, Stratus High-Level Synthesis, Genus Logic Synthesis, and Cerebrus AI. By leveraging this integrated approach, significant enhancements in schedule adherence, agility, area efficiency, power optimization were achieved for a high-speed 2GS/s UWB transceiver design and a RADAR coprocessor.

Air Force Research Laboratory (AFRL) 

As mission-critical systems grow in complexity, Model-Based Systems Engineering (MBSE) becomes essential for validating top-level specifications and ensuring traceability down to detailed hardware, firmware, and software designs. However, engineering teams face challenges due to fragmented MBSE assumptions about functionality, performance, security, and digital thread continuity. This fragmentation leads to compounded errors across different tools. While development teams use specialized tools for tasks such as electronic design automation, verification, and design, systems engineers rely on platforms like DOORS, Cameo, and Rhapsody to manage requirements and develop SysML diagrams (e.g., use cases, structure, sequence, state).

A fundamental issue arises from the existence of two disconnected authoritative sources of truth (ASoT). Although ASoT spans multiple tools, gaps between them create inconsistencies and "one fact, one place" violations. Improving traceability from system definitions to software and hardware design is critical to resolving these discrepancies. The emerging SysML V2 standard offers enhanced traceability, usability, and interoperability compared to SysML V1, presenting an opportunity to bridge these gaps.

This paper explores the integration of hardware-accurate digital twins (HADTs) with system-level models using SysML V2 and its robust APIs. Key actions include developing hardware-accurate digital twins, leveraging SysML V2 APIs to establish a complete digital thread between system and design-level tools, and addressing the complex many-to-many mapping between MBSE and HADT models. By adopting this approach, organizations can create an integrated digital thread, establish a consistent ASoT, and accelerate system maturity earlier in the development lifecycle—ultimately leading to more reliable, functional systems.

Ezekiel Wheeler

My Desktop Satellite Tracker uses a magnetometer and accelerometer for position sensing. Based on the research detailed in related work, this has never been done before. These sensor components allow for accurate satellite tracking with minimal calibration, which I show to work with small and large scale tracking assemblies. This is a new application for these components. In this paper, I present the design, proof of concept, methodology, testing and accuracy results for a desktop-sized satellite tracker, in addition to a full size satellite tracking system; both utilize the same technology. Using my full size satellite tracking system, I was able to track the International Space Station and facilitate a conversation over amateur radio with an astronaut.

Intel

As part of Intel’s drive to open Intel fabs to external customers, Intel memory compilers are enhanced to provide memory models that support all major EDA tool flows. This includes CMV model support for the Cadence Genus/Modus based DFT flow. Within this effort, eight leading edge Intel memory compilers now generate validated CMV memory models on Intel’s leading edge 18A process. Generating memory DFT models is only the first step in the process. Most of the effort involves validating the DFT models to ensure they are correct. This presentation will start with a brief overview of DFT memory models, the Cadence Genus/Modus flow and CMV models. It will then cover the approaches developed to quickly validate behavioral and structural aspects of CMV models. For example, for CMV structural model validation, we compare address-based bit cell positions from compiler generated bitmaps against address-based bit cell position files generated by Genus from CMV models. This approach checks any address-based row and/or column reordering that would shift bit cell positions. Correct modeling of row-to-row adjacency and column to column adjacency, is needed for more effective memory test pattern generation. For CMV behavioral validation, we use a customized Cadence Rapid Adoption Kit (RAK) script to drive the Genus/Modus flow to generate test benches and test patterns that target one memory at a time. This simplifies flow automation and reduces run times while minimizing potential debug efforts. Complete model validation run times average 4 minutes/memory, and we validated more than 500 memory configurations per compiler. The Cadence user community can apply similar CMV validation strategies to their own custom memories and/or compiler memories before integrating them in their SOC design projects.

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

proteanTecs

Silent Data Corruption (SDC) poses a growing threat to AI processors, escaping conventional detection methods and undermining hardware reliability. As AI workloads become more compute-intensive, undetected processor faults can lead to incorrect computations, cascading failures, and unpredictable system behavior. Traditional silicon testing methods, including scan, ATPG, and functional testing, fail to catch the subtle anomalies that cause SDC, making in-field monitoring essential. With hyperscalers reporting hgher SDC rates, the need for a proactive, multi-stage detection approach has never been more critical.

proteanTecs introduces a two-stage solution to combat SDC: telemetry based Outlier Detection, which enhances SoC testing with ML-powered parametric analysis to identify at-risk chips before deployment, and Real-Time Health Monitoring (RTHM), which continuously tracks chip performance in the field to detect and prevent emerging faults. By leveraging deep data insights, real-time monitoring, and predictive analytics, proteanTecs' technology reduces SDC occurrences, enabling AI processors to maintain reliability at scale. This approach shifts the paradigm from reactive troubleshooting to proactive prevention, ensuring that AI systems can operate with high integrity and confidence.

This presentation will review the Cadence implementation workflow for integrating proteanTecs on-chip monitoring solution, in use today at leading semiconductor companies. Leveraging Cadence tools, novel methods are employed to implement proprietary Agents (IP). As a provider of both soft and hard IPs that are inserted into an existing functional design, proteanTecs streamlines the integration process by the user through the use of Cadence solutions. This collaboration delivers a holistic approach to ensuring AI processor reliability in the face of increasing complexity.

Secure-IC SAS 

Chiplets enable considerable gains in agility, scaling, and TTM. To unleash the full potential of this promise, it is required that the various chiplets be trusted in terms of provenance. An incorrect mix and match of inconsistent or even rogue chiplets would undermine the viability of the approach. Hence caring about cybersecurity is a prerequisite.

In this presentation, we adopt an analytical posture to address the question of System-in-Package (SiP) trustworthiness. We show that existing cybersecurity functions can be leveraged to emerge secure chiplets aggregation. We also demonstrate that the solution can be implemented as part of a reference chiplet architecture, as provided by Cadence Silicon Solution Group (SSG) / Compute Solutions Group (CSG).

The SiP will be trusted if two properties are safeguarded: Hardware & Software Bill of Material (HBOM and SBOM) secure provenance and integrity.

In a risk analysis approach, we MUST consider threat agents. Their exact nature and intentions are hard to predict exhaustively, but let us give some examples:

- Nation states attacks exploiting the supply chain;

- Incorrect HBOM or SBOM leading to configuration errors thereby voiding safety guarantees;

- Economic fraud abusing the chiplet business model, through supply of lower PPA chiplets or overbuilding.

For those reasons, security is a system-level overarching requirement.

It is mostly a cybersecurity (security orchestrated at logic level) topic, which nonetheless should be reinforced by a physical security dimension as attackers can procure chiplets from the open market to train their attacks (reconnaissance phase).

Cadence partners with Secure-IC to offer to their Customers the best-of-breed security solution, which has been proven suitable for chiplets.

It is backed on multicertified IPs and vetted cybersecurity concepts:

 - security by default, hence end-to-end security, from pre-silicon to mission mode, incl. through delegation

 - fail secure, i.e., whatever happens, the S500 solution does not compromise the security

 - resiliency: the system does not brick in case of an issue (bug or attack), but leave it possible for the user to recover through diagnose services

 - minimality of the design, to allow for agnosticity wrt use-cases

 - defense in depth (e.g., software no touch key, or Internal Key Generation)

 - capability to debug securely

 - capability to manage (multi-domain) power securely

 - pre-compliance by activating configuration items

Arm

The growing complexity of system-on-chip (SoC) designs and the demand for scalable, high-performance solutions have ushered in a new era of innovation with chiplets. We will explore the exciting opportunities unlocked by chiplet-based designs, emphasizing the need for collaboration to enable chiplet interoperability.

We will introduce the Arm Chiplet System Architecture (CSA), detailing its role in enabling modular, scalable designs that tackle challenges in performance, cost, and time-to-market. CSA enables greater reuse of components (physical design IP, soft IP etc) between multiple suppliers. It helps standardization efforts around system design choices for different chiplet types, such as how to partition an Arm-based system across multiple chiplets, or their high-level properties.

Cadence will highlight its successful chiplet tapeout, a compelling case study and the industry’s first Arm CSA-compliant base system chiplet, showcasing its capabilities and potential applications. We will discuss this scalable chiplet architecture and Cadence’s flexible engagement model that realizes the benefits of chiplets, including accelerated development cycles, greater levels of integration and improved system flexibility.

Join us to gain insights into how Arm and Cadence's collaboration is pushing the boundaries of semiconductor design, setting the stage for a future defined by smarter, more adaptable technologies.

Secure-IC SAS 

Having devices be "secure" is no longer an option or a nice add-on, but an explicit requirement.

Market if not regulation is pushing.

To comply to expected security requirements by the deadlines, proactive action is required now.

To give two compelling reasons: migration to post-quantum cryptography for managing low-level firmware lifecycle is due now (2025) and is mandatory by 2030, as per CNSA 2.0 roadmap.

Also European Cyber Resiliency Act (EU CRA) demands that devices security be managed by Sept 11 (!) 2026, and that they fully comply by Dec 11 2027.

In this context, ramping up with security technologies is a priority in the design of any digital system. One can distinguish between pre-silicon and post-silicon phases. Pre-silicon, consists in planning for the implementation of a Hardware Root of Trust.

Why hardware? Simply because otherwise the security features can be subverted by so-called supply-chain attacks. Hardware protection, as referred to as "immutable" protections, are the only ones that cannot be hijacked during the different stages of product manufacturing. The graal in this respect is the pre-silicon binding of the yet-to-be chip with the manufacturer, which is typically achieved by engraving fingerprint of the manufacturer inside of the design ROM. This way, only the licit manufacturer is authorized to provision the device, in a fully end-to-end manner whatever the supply chain happens to be. After product release in mission mode, post-silicon security consists in enabling monitoring and updates, either being trustworthy owing to the pre-established hardware root of trust. It therefore appears very natural that the overall security of a product stems from its early design stages.

In this presentation, we provide a testimony that Cadence EDA tools and IP are already set to accompany customers into securing their projects.

At EDA level, the point is to show how they assist in the implementation of security functions, and check for the absence of regression whatsoever during the refinement phases. At IP level, it is paramount to offer a portfolio of options for hardware root of trust, such as integrated Security Elements (iSE) capable of various services and empowered to sustain security in various adversarial contexts.

In this talk, Cadence and Secure-IC will illustrate how embracing embedded cybersecurity is natural throughout product design, from hardware stage to deployment of the software stack.

Intel/Cadence

The Universal Chiplet Interconnect Express (UCIe) standard is evolving rapidly, driving the need for robust interoperability testing to ensure seamless integration across diverse chiplet ecosystems. In this talk, we will present the latest interoperability results from Intel and Cadence, demonstrating how our collaborative efforts enhance UCIe adoption.

We will explore interoperability at multiple levels, highlighting the critical role of concurrent interoperability testing in accelerating protocol validation. By integrating interoperability testing early in the development cycle, we align with a shift-left strategy, reducing design iterations and expediting time-to-market for UCIe-based solutions.

A key highlight of our discussion will be a novel interoperability method used by Intel and Cadence. This approach enables real-time interoperability testing without sharing confidential data, mitigating the complexities of encryption while lowering costs and engineering effort. This breakthrough technique offers a scalable framework that can extend beyond UCIe to other interface IPs, fostering a new paradigm for cross-company interoperability.

Join us as we showcase how structured, concurrent interoperability testing can drive the future of chiplet-based architectures, ensuring that emerging standards remain both flexible and interoperable.

Intel Foundry 

AI is changing the world, and semiconductors serve as the foundation of the new AI Era. Semiconductors are driving innovation across cloud to edge and beyond, addressing compute challenges by showing gains in energy-efficiency, performance, cost, and more. This ever-evolving need for innovation to power the AI Era is transforming industry globally. 

With an eye on meeting today’s requirements and preparing for future innovation, the collaboration between semiconductor manufacturing and the design ecosystem plays a pivotal role in bringing customers’ products to market and allowing them to differentiate through their designs. This presentation will highlight how Intel Foundry and Cadence are collaborating to drive breakthroughs on process, packaging, tools, solutions and IP to not only address current market challenges but to enable their mutual customers to succeed.

SiliconScapes 

Cadence Tensilica DSP are known for their ability to be extended with custom instructions and operations to achieve the best performance and performance-per-watt for compute-intensive applications.  The Tensilica Instruction Extension (TIE) language empowers designers to create true bespoke processors that are purpose built to accelerate performance critical algorithms and kernels. Moreover, the Tensilica family of DSP allow custom hardware accelerators to be tightly coupled through high-bandwidth and low-latency external interfaces.  According to the requirements of the accelerator, these interfaces can be based on queues, fixed latency lookups, or Tightly-Coupled-Memory (TCM) sharing.  In this presentation, SiliconScapes will detail our experience in configuring and integrating Tensilica DSP into complex SoC designs that are comprised of multiple heterogeneous cores and custom hardware accelerators.  The presentation will focus on our approach to two aspects of designing with Tensilica DSP. 

First, we detail our approach to selecting the ideal interfaces for integrating various hardware accelerators with Tensilica DSP.  The presentation will highlight SiliconScapes’ approach to designing and integrating hardware accelerators through use cases that are representative of our design experiences with clients in the LiDAR and AR/VR domains.

Second, we describe our methodology for integrating Tensilica DSP into subsystems that can be easily incorporated into larger multicore silicon platforms.  We note that a key objective in the integration flow is early hardware/software co-simulation of the DSP along with a diverse cast of peripherals, hardware accelerators, application processors, memory, and DMA engines.  One challenge is that once a DSP is generated by the Xtensa Processor Generator, the different hardware accelerators typically exist at varying stages of completion, ranging from algorithmic/system modeling to functional RTL.   SiliconScapes will illustrate how it leverages its in-house co-simulation environment, CoreSYMU, to simulate Tensilica DSP with system infrastructure and hardware accelerators, regardless of their state of implementation. 

SiliconScapes is a hardware and software design consultancy that specializes in Tensilica processor technology.  Our expertise includes Tensilica DSP configuration and integration, hardware accelerator design, FPGA prototyping, and hardware/software co-simulation of processor-based systems.

Cadence

With the advent of Agentic AI and Generative AI, datacenter architectures have been transformed into AI clouds and factories, igniting a revolution in the computing industry. This surge in HPC and AI demands cutting-edge SoC, chip to chip, and module architectures that cater to these innovative spaces. As the call for heightened performance and computational prowess grows, standards bodies and IP implementers are stepping up, crafting solutions for xPU designs to scale-up and scale-out. We'll delve into crucial memory standards like the latest LPDDR and HBM versions, alongside key interface standards such as 112G/224G, UALink, Ultra Ethernet, PCIe, and CXL, and chiplet and die-to-die interfaces like UCIe, which are pivotal to these new architectures for HPC and AI products. Join this talk to uncover the unique architectural requirements and discover how the right IP selection can pave the way for successful designs.

Attotude 

Quantus & EMX Solver are trusted tools for accurate post layout simulation of designs spanning from low frequency analog to mmWave and beyond frequencies. Quantus is a trusted RC extractor for accurate and fast post layout simulation of designs where the dimensions are well below 1/10 ????, including tightly coupled, physically small geometries (fingers) and base layer structures, e.g. FETs and HBTs. Quantus is also widely supported and validated by fab houses for their PDKs. 

The EMX Planar 3D Solver is the “go-to” EM Solver for full extractions of RF and mmWave passive structures as it accurately includes their inductive parasitics and coupling. Such passive structures encompass inductors, transformers, t-coils, transmission lines and metal interconnect, with dimensions that span 1/10 ???? and higher.

For high frequencies approaching mmWave, combining Quantus & EMX in a hybrid approach will utilize the strengths of both tools, while minimizing the weaknesses. This is essential in today’s highly integrated designs where feature sizes can vary over a wide range. When combining these tools, picking the right separation or ‘cutoff’ point is not always straight forward. By black boxing the Quantus extraction for base layer and lower metal layers, we can realize this approach and improve accuracy. This hybrid approach can help provide the most accurate simulation results at mmWave frequencies and can improve design efficiency and accuracy.

The proposed hybrid approach was successful in achieving an accurate, post layout simulation of a cascode HBT cell for use in an amplifier. This was critical when optimizing the layout parasitics for the highest Maximum Available Gain (Gmax) at the frequency of interest. The model consisted of creating a Quantus RC extraction for the base layer and all “thin” BEOL layers. The remainder of “thick” BEOL layers were simulated using the EMX Solver, with the Quantus RC extracted portion black boxed. This created a self-contained, accurate model to develop around.

The Boeing Company / Boeing Research & Technology 

The ability to understand the thermal impact on performance has become a necessity for today’s complex electronic designs. Having an integrated thermal analysis tool within a multiphysics system design flow proves to be very beneficial for determining overall performance and becomes necessary to maintain design flow synchronization. This paper demonstrates the capabilities of the Cadence Celsius Studio platform as an electrothermal co-simulation solution that provides thermal analysis and chip through system level design insights to detect and mitigate thermal issues early in the design cycle. Simulations are validated with measurements on devices designed for thermal imaging and current density performance. 

Thermal management is a critical challenge for all areas of the design flow. Whether the design is at the Integrated Circuit (IC) or Printed Circuit Board (PCB) level, the impact on performance from thermal degradation affects the whole system. Early simulation tools did not have the capability to accurately predict the thermal profile of devices and structures without having to produce structures to verify estimates of the impact to various designs. Substantial work has been incorporated into the  device models we use today as well as the material stackup definitions that are used. Depending on the technology used there are several techniques and topologies used to help with the thermal stability, mitigation, and electrical performance of the active devices. Additionally, there are numerous efforts undertaken to develop a model that would predict the self-heating effects of the active devices. This paper will show the methodology used to reduce the design cycle by avoiding performance impact caused by thermal degradation.

NXP

Next generation Edge Artificial Intelligence (AI), Internet-of-Things (IOT), Industrial and Automotive Networking microprocessors have high performance requirements without having to compromise on the overall system cost. These applications require large memory capacity with low latency, improved power delivery network (PDN) and high Input/Output (I/O) pin count to control the peripheral devices. Using Chiplet package technology the memory interface and passive devices needed for improved PDN can be integrated using fan-out package technology and final connection to PCB can been implemented through low-cost Substrate-Like-PCB (SLP) technology for cost-performance optimization. Preserving the signal integrity of the high-speed interfaces is crucial while adapting to new package technologies. To analyse the performance of the transmission lines, Cadence Sigrity XtractIM has been used in the past for the RLC model extraction.

For the high-speed analysis of DDR and SerDes buses, one of the main challenges was choosing the right modelling environment and settings given the complexity of Chiplet stackup. After looking into different options,  Cadence Clarity 3D Full Wave FEM tool has been chosen for  the S-parameters extraction. The authors intend to show how Clarity scales with problem size and available computer resources, and why it is the tool of choice for advanced Chiplet package architectures.

Amazon Project Kuiper 

System design engineers face increasingly difficult power distribution network (PDN) design targets, with varying design and hardware delivery dates for chips, packages, and PCBs. Ensuring a functional PDN under these conditions is challenging. This paper explores the spatial, frequency, and loading effects of a system on PDN target impedance requirements. Two power delivery strategies are examined: single point-of-load PDNs and PDNs feeding multiple parallel loads. The required bandwidth (BW) of the PDN response depends on the supply network location. The paper aims to correlate Cadence PowerSI simulations with VNA measurements to determine bandwidth changes with major PDN components from the DC source pads to IC pads on the PCB. It highlights that impedance requirements differ across the system due to spatial filtering effects. Power integrity experts must decide whether to combine power rails or provide separate power for each device. Using two high-power processor-based server systems, the paper measures and simulates power rail impedance at various PDN points. The findings offer guidelines to avoid over-designing PDNs and to understand considerations for complex multi-load power deliveries.

Teradyne

With the growing complexity of high-speed PCB designs, the traditional signal integrity (SI) optimization methods are increasingly time-consuming. To address these challenges, we proactively introduced Cadence Optimality Explorer, an AI-driven optimization engine, for PCIe Gen4 channel breakout optimizations in one of our key projects. By leveraging the Optimality-empowered Clarity 3D Solver, we significantly reduced the time spent optimizing transmission line performance. This AI-driven optimization helped us quickly identify the best physical parameters for high-speed differential pair routing constraints by efficiently determining the optimum TDR waveforms, return loss, and insertion loss. Consequently, our team’s productivity increased, contributing to project acceleration while maintaining design quality. Additionally, this innovative approach helped achieve a highly successful EAS (Early Access System) with a key customer and made this project one of the fastest EAS designs to get to the customer. This presentation will detail the approach and highlight key features, practical benefits, and the impact on our design process.

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

PCB Automation / Cadence 

This session will discuss the process required to develop a working UCIe interface that is featured in a Cadence IP test package.  Attention will be paid to the UCIe interface specification and what is required of design and analysis tools to help design teams efficiently meet the specification. 

The presentation will walk you through the steps utilized to integrate Cadence chiplets with UCIe PHYs into various package types including a standard organic package as well as an advanced package including a silicon interposer. The presentation will conclude with a demonstration of how Cadence tools were used to create an industry compliant UCIe interface.

Wild River Technology

The “need for speed” in AI systems is driven by their requirement to process large data sets, both during training and application. Channel design for is constrained by the balance between acceptable loss budget and power consumed in equalization and error correction. Reducing channel loss can enable lower power or longer unrepeated channel lengths. Historically, high-speed serial links focused on material selection to manage attenuation. In 224 Gbps PAM4 systems, however, second-order factors like impedance variations, cross talk, and power loss into cavities significantly impact the loss budget.

While perfectly transparent virtual channels can be designed in simulations, real fabricated boards differ due to manufacturing variations and limited understanding of material anisotropy. As channel bandwidths increase to 56 GHz and above, accurately defining material behavior in simulations becomes crucial. This paper analyzes second-order design features using precision measurements of test vehicles. We propose a metric-driven methodology based on AI/ML to determine relevant parameters for simulating anisotropic behavior that matches both time and frequency domain measurements.

When second-order factors are accounted for, accurate measurement-simulation correlation is possible, enabling the design of digital twins that predict system performance. These digital twins, combined with AI/ML techniques, allow for design space exploration and sensitivity analysis to identify manufacturing tolerances necessary for creating 224 Gbps PAM4 channels with acceptable total loss. This process highlights the importance of characterizing anisotropic dielectric properties and including them in simulations to achieve better than 2% measurement-simulation correlation in impedance profiles. This approach allows for optimized geometries and controlled geometry designs.

ZF

The increasing use of MIPI (Mobile Industry Processor Interface) standards in automotive applications has made signal integrity (SI) essential for reliable performance in high-speed data transmission. The unique challenges posed by automotive environments, such as electromagnetic interference (EMI), temperature variations, power fluctuations, and PCB design constraints, can degrade the quality of MIPI signals. 

With an emphasis on crucial elements like trace routing strategies, impedance control, differential pair design, termination tactics, and power integrity considerations, this paper examines best practices for maximizing MIPI signal integrity in automotive applications. The function of Aurora simulation in anticipating and preventing SI problems is also covered, offering engineers a framework for effectively analyzing and improving MIPI interfaces. 

In automotive MIPI-based designs, engineers can improve overall system robustness, minimize signal loss, reduce crosstalk, and improve data reliability by implementing these best practices and Cadence Aurora features. This will ensure long-term performance stability and compliance with Automotive industry standards.

OLogic 

OLogic has successfully integrated the Cadence Sigrity Suite into our design methodology for years, leveraging its powerful analysis tools to ensure signal and power integrity in our PCB layouts. By incorporating Sigrity into our workflow alongside Altium Designer, we can make critical layout adjustments before fabrication and confidently validate high-speed interfaces for our customers. In this talk, we will walk through the design process of the Pumpkin Genio 700, the latest in the Pumpkin Genio series developed in partnership with MediaTek, demonstrating how we applied Sigrity tools to validate key high-speed peripherals such as MIPI, HDMI, and DDR4 memory. We will detail our approach to signal and power integrity analysis, highlighting how these workflows enable us to create reliable, high-performance designs before a board ever reaches production.

Samsung

As semiconductor complexity continues to rise, driven by the increasing demand for AI chips and hyperscaler applications, maintaining power integrity has become a crucial aspect of chip design. This paper explores the application of Cadence Voltus InsightAI, an AI-driven in-design solution that utilizes generative AI technology to address power integrity issues through early prediction and automated IR drop closure. By integrating seamlessly with the Cadence digital full flow, Voltus InsightAI provides a comprehensive environment for improving power, performance, and area (PPA) metrics specifically tailored for Samsung Foundry's advanced process technologies.

In this context, Voltus InsightAI enhances the design process by predicting potential IR drop issues early, allowing engineers to implement proactive measures that are crucial for maintaining performance at scale. Notably, results from applying this tool in the high-speed CPU chip using Samsung's SF2 node demonstrate its effectiveness in identifying and automatically fixing IR-drop violations. The application achieved an impressive 99.7% resolution of IR-drop violations without any performance degradation, showcasing the tool's ability to balance power integrity with performance needs.

Voltus InsightAI seamlessly integrates IR drop fixing into the P&R flow through two key steps:

 1. Pre-Route IR Fixing (Post-CTS Phase)

  Identifies and mitigates potential IR drop issues after the Clock Tree Synthesis (CTS) stage. Strengthens power integrity early, reducing the risk of violations during routing.

 2. Post-Route IR Fixing (Final Optimization)

  Optimizes the post-route database to further refine power integrity. Fixes any remaining IR drop violations that emerged during routing, ensuring a robust power delivery network.

 By addressing IR drop in both the pre- and post-route stages, Voltus InsightAI ensures a robust, reliable design, paving the way for higher performance and efficiency in the final design.

The solution's automated fixes facilitate rapid IR drop closure, significantly boosting productivity and reducing iterative design cycles. Additionally, the tool's capabilities are grounded in timing and design rule checking (DRC)-aware adjustments, ensuring compliance with Samsung’s stringent design specifications.

Cadence

Explore how Cadence leverages its Cadence Reality Digital Twin Platform to enhance data center lifecycle management with a focus on performance and sustainability. This presentation details Cadence’s two-year roadmap, showcasing how the platform delivered substantial energy cost reductions and positioned the data center for future application density increases, effectively postponing capacity expansions that were previously unattainable.

NVIDIA

With the explosion of generative, agentic, and physical AI, the next industrial revolution has begun. Companies and countries are shifting from trillion-dollar traditional data centers to accelerated computing with a new type of data center — AI factories. Join Cadence and NVIDIA experts to learn about the role of AI factories and the challenges in designing, building, and operating these new facilities. Explore how advanced physics-based simulations powered by Cadence Reality Digital Twin, NVIDIA Omniverse, and OpenUSD, enable data center teams to design these complex AI factories at scale with greater efficiency and optimized performance. Get briefed on how the broader data center ecosystem can support these efforts and accelerate AI-powered innovation for every industry and field.

•    How simulation enables AI factory design and addresses common operational challenges and inefficiencies

•    How NVIDIA is using advanced simulation capabilities from Cadence to simulate and design next-generation AI factories at scale for greater efficiency and optimized performance

•    How the broader data center ecosystem, including partners like Foxconn and Vertiv, is enabling the design and simulation of AI factories

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

General Motors / Cadence

The interior safety properties of automobiles have been subject to increasingly stricter requirements under occupant protection legislation. The US laboratory test procedure known as FMVSS201U specifically focuses on head protection during impact with the upper interior components, and requires identification of critical targets, upper roof zone, and headform impact angles. To reduce the need for physical tests, manufacturers use CAE software for product performance evaluations as much as possible. However, due to the sheer number of potential load cases, an infinite number of simulations would be necessary to cover all possibilities. As a result, flexible tools are needed that not only allow the analysts to automate their processes, but also enable them to intervene at any stage, make modifications, and assess their impact.

General Motors, in collaboration with Cadence Company, BETA CAE Systems, has upgraded their target marking process according to FMVSS201U. This has resulted in the achievement of fully automated identification of the desired targets in the upper interiors, as well as the ability to intervene and make modifications to auxiliary data at any step of the process. This is applicable in both FE and CAD data building, bridging the gap between analysts and designers. Additionally, a detailed and robust positioning process has been established to cover all the demanding specifications of the protocol. Finally, ready-to-run load cases for LS-DYNA are created in bulk for all target points.

The presentation provides a comprehensive explanation of the process and showcases how ANSA has met the needs of General Motors in their FMVSS201U process. The presentation also includes metrics that demonstrate the correlation between testing and simulations, offering insight into the added value that BETA and General Motors have gained from their collaboration on the ANSA tool.

University of Nevada, Reno

This study investigates the unsteady flow physics of a finite NACA-0015 wing undergoing forced pitching. Simulations are performed using Fidelity CharLES across a range of low to moderate Reynolds numbers at a constant equilibrium angle of attack of 15 degrees. We analyze variations in flow characteristics—including vortex dynamics, wake development, and aerodynamic loads—by altering the frequency and amplitude of pitch oscillations. By examining energy map contours from these simulations, we aim to identify aeroelastic flutter boundaries, providing valuable insights for flutter prediction and control in aerodynamic applications.

Cadence

The next order of magnitude boost in productivity in electronic design and analysis is being brought about by AI-enabled technologies. Blending with traditional methods and investing significantly in research, Cadence has pervasively adopted AI to assist designers in exploring much larger solution spaces while optimizing to exacting standards and aggressive goals. As design complexity begins to exceed limits of traditional methods and tools and market demands compress turnaround times, disruptive changes through automation are likely to require adoption of new methodologies, while assuring consistent quality of results. This talk helps paint a vision of that future, while sharing credible metrics of current state of innovation that have started to demonstrate incredible results.

The Provenance Chain Network 

The growing complexity of modern computing platforms, coupled with the increasing need for Intellectual Property (IP) protection, counterfeit detection, SCRM (Supply Chain Risk Management) sustainability, and regulatory requirements, necessitates innovative approaches to data exchange between parties in a zero-trust environment. Producing a digital representation of device metrology, material, physical and electrical properties, C02e (Carbon Dioxide Equivalent) content, and design rules requires connecting data sets from multiple disciplines using multiple industry standards for multiple participants in the flow. These datasets often contain sensitive IP, materials and assembly information.

The Electronic Datasheet (EDS) specification, developed by an industry consortium that includes Cadence, Google, Intel, The Provenance Chain™ Network, Nexperia and others, and released in 2024 helps make this possible. The EDS enables domain-specific ingredient information to be connected to form a digital twin that can be included in a secure product development flow, spanning from design to end-of-life or recycling, and building an immutable record of the people, products, processes, parties and places involved. Creating a secure, resilient, permissioned environment that leverages the descriptive power of the EDS and encompasses all phases of the product lifecycle, while protecting Intellectual Property, is achievable by using Distributed Ledger Technology (DLT) and Blockchain technologies. Requirements, Incentives, Claims and Evidence (RICE™) is implemented in a set of protocols on the distributed ledger by The Provenance Chain™ Network, and records, enriches and enables sharing of immutable data securely between parties.

This session will present a practical application of DLT and Blockchain Technologies and protocols to create a secure supply chain implementation that leverages the power of the EDS. This application is currently being adapted as part of NIST Grand Challenge #7 for Security and Provenance of Microelectronic Components and Products. The presenters will show how digital assets can be registered on the blockchain and accessed by design engineers, procurement specialists and regulatory compliance verifiers, as well as LCA (Life Cycle Assessment) specialists to support emerging Digital Product Passport requirements.

Intel

Enhancing System Design with Standardized Electronic Data Sheets (EDS) and the Traveler Concept

With increasing complexity in system design, simple errors can have significant financial and scheduling consequences, often determining a product’s success or failure. Leveraging standards-based, comprehensive component information allows designers to seamlessly integrate new components and identify potential issues early in the development cycle, significantly reducing costly iterations and delays.

In collaboration with Cadence, Intel, and Independent Hardware Vendors (IHVs), we introduced the standardized Electronic Data Sheet (EDS) for the PC platform, capturing essential electrical, configuration, and physical device characteristics. This standard enables unprecedented automation, drastically reducing mistakes and enhancing overall product quality. Open-source tooling now exists to facilitate the creation of specification-compliant EDS, streamlining component integration and verification tasks.

This year, following extensive collaboration and community input, the EDS has evolved and expanded into seven key sections:

- 3D Mechanical Model

- 2D Land Pattern Model

- Logical Model

- Simulation Model

- Interface Constraints

- Life Cycle Analysis (LCA) Information

- Supply Chain and Materials Data

Additionally, we are introducing the "Traveler" concept, an innovative container designed to manage multiple EDS documents, enhancing data organization, traceability, and usability across the product lifecycle.

This presentation will highlight these significant enhancements, demonstrate practical applications, and outline how designers, engineers, and component manufacturers can contribute. We will also discuss the EDS roadmap and illustrate how Cadence and Intel are driving integration of these advancements into System Capture, enabling intelligent, efficient, and error-free design.

Qualcomm

RAVEL is used for writing custom DRCs checks for Package and PCB designs in Allegro based tools such as APD+ and Allegro X. This presentation will show how RAVEL can be used for validating design against checks that are not available within APD+ out of the box. Details will include RAVEL syntax, capabilities and execution.

Circuit Mind

Since the launch of ChatGPT, AI has revolutionized our personal and work lives. Yet, for professional electronic engineering teams, the promise of AI has remained elusive — The absence of trusted, reliable AI solutions tailored for real-world design augmentation has left a gap. Until now…

In this session, discover how Circuit Mind is empowering Cadence customers on real-world designs to move from architecture to optimized Bills of Materials (BoMs) and schematics in System Capture and OrCAD in mere minutes, accelerating time-to-market, minimizing costly respins, and enabling the creation of smaller, cost-effective, and power-efficient products.

Learn how to left-shift your design process, optimise over billions of component combinations, avoid datasheet doom-scrolling, reduce schematic errors, design for supply chain and reliability in minutes with Circuit Mind’s algorithmic component selection and schematic generation technology.

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

Celus

How do you take your ideas and requirements and translate that data into a complete bill of materials (BOM) and full EDA environment? See how you can “Design with AI”. Start with your idea and requirements in the form of functionalities and functionality specifications. Then, learn how the CELUS Design Platform automatically provides sets of electronically-correct solutions. With those selections, the CELUS intelligent platform produces a complete BOM and outputs to Cadence’s OrCAD X design environment.

Cisco

Artificial Intelligence (AI) is rapidly developing, driven by the capabilities of hyperscale data centers. Silicon photonics offers a cost-effective solution for optical interconnects used in these data centers, but designing these systems requires careful consideration of both optical and electrical components. Traditionally, optical and electrical ICs are designed separately and then packaged together. However, with data rates approaching 1.6 Tbps, the interference between electronic and photonic ICs in the same package becomes significant, necessitating optimization of the individual ICs at the package level during the design stage.

The latest developments in Cadence’s Virtuoso Studio addresses this challenge by enabling the co-optimization of ICs from two different technologies within a unified environment. In this work, we used Virtuoso Studio and EMX integration to analyze the impact of photonic IC on the performance of the LC-VCO in the electronic IC. We will present the Virtuoso EM (VEM) flow and compare it to the traditional flow, demonstrating the importance of co-optimization in optical interconnect development.

Cadence

Get a sneak peek at upcoming developments in the Virtuoso Studio and Spectre platforms, including work done in support of Agentic AI. The enhanced technology encompasses all aspects of Custom IC design and will be relevant for photonics engineers. In this session, we will be emphasizing updates to our Virtuoso Studio Photonics platform and new capabilities within our high performance RFIC design suite.

Intel

An optical path, defined as a connected sequence of design IPs, constitutes a critical component of photonic integrated circuit design. This can be an optical path between an integrated laser source and an edge coupler or between two grating couplers used for characterizing a PIC component. We will demonstrate how a typical optical path can be extracted by leveraging properly implemented PIC components in the Virtuoso Electronic Photonic Design Automation (EPDA) solution. This includes interactive and automated extraction in the schematic and layout leading to the final proposed solution.

In the final implementation, a graph representation of a PIC design is extracted, and a supervised machine learning traversal method is discussed; the method is then used to traverse the PIC design's graph. The proposed solution is applied to extract an optical path in an Optical Compute Interconnect (OCI) design between an integrated laser and an edge coupler, significantly decreasing the extraction time. Practical applications of this solution in Wafer-level Test (WLT) and Optical Back Reflection (OBR) are also discussed.

Wave Photonics

The energy and bandwidth challenges faced by data centers, and the growing demands of AI model training have driven a huge increase in demand for silicon photonics and Photonic Integrated Circuits (PICs). This demand will drive volume and process maturity, which can then be leveraged by novel PIC applications, such as quantum technologies and consumer healthcare.

Wave Photonics aims to facilitate this revolution by providing highly optimised, fabrication tolerant, multi-fabrication-process, and multi-wavelength process development kits (PDKs), allowing users to focus on circuit design rather than component modelling and iteration. Users can access our PDKs through the Virtuoso platform, which enables both circuit simulation and scriptable layout design, tools which are becoming essential as circuit complexity increases. This is all made possible by the SKILL programming language, and the CurvyCore API used by Virtuoso, which renders it fully programmable for photonics applications.

This talk will outline Wave's Virtuoso integration, and present case studies for its use in PIC design.

GlobalFoundries

An electronic photonic reference flow for a 4x4 optical switch circuit has been developed using Cadence EPDA for 45SPCLO technology. The reference flow contains design descriptions, recommendations and guidelines along with model to hardware-correlated data, which strengthens the trust of customers with the GF PDK and design flows. The optical switch circuit used for establishing the reference flow was taped out and measured prior to this work. Simulation intricacies, Layout generation, physical verification steps (LVS & DRC). Corner and Monte-Carlo analysis have been developed and all the features of GF FOTONIXTM PDK have been put together to allow customers to accelerate their design process using GF PDK features, supported software tools, and recommended methodologies. The circuit simulation has been performed in Virtuoso Spectre and the output was compared with hardware result as well as PDK model-based simulation result.  A strong model-to-hardware correlation for the spectral response, insertion loss and crosstalk of the switch has been obtained.

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

Mixx Technologies

AI is rapidly redefining the next generation of data center architecture and compute - straining existing technology roadmaps and capacity. Specifically, scale-up, the connection between GPUs, drives massive interconnectivity densities and speeds that the current electrical based ecosystem is struggling to meet. Integrating optical interconnects using advanced packaging offers significant benefits but also presents critical challenges. Benefits include higher bandwidth density, reduced power consumption, and improved scalability compared with copper. However, challenges such as thermal management, precise alignment of optical and electrical components, and maintaining signal integrity in compact layouts must be addressed. Design and Manufacturing scalability is hindered by complex fabrication processes, impacting cost and yield. Overcoming these challenges is essential for unlocking the full potential of optical interconnects. In this paper, we present the challenges from EDA co-design, system analysis and co-simulation.

Flexcompute

Designers of photonic integrated circuits (PICs) face lengthy simulation times when using CPU-based electromagnetic solvers to design and optimize photonic components. Additionally, transitioning from component-level simulations to system-level simulations and generating layouts for manufacturing is non-trivial. Traditional workflows require manual export and import processes, increasing the risk of errors and extending development cycles. To address these challenges, we introduce the PhotonForge Connector, which seamlessly integrates Flexcompute's GPU-accelerated simulation platform with Cadence Virtuoso, providing a streamlined electronic-photonic design automation flow.

The PhotonForge Connector enables designers to effortlessly transition from Virtuoso layouts to 3D electromagnetic simulations. By extracting layout geometries, GDSII layer information, and PCell parameters directly from Virtuoso, the connector automates 3D extrusions and simulation setup. This process is further streamlined by Flexcompute’s collaboration with leading foundries, ensuring accurate layer stack information and fabrication-ready designs.

For Cadence Virtuoso users, this integration not only accelerates simulation times, achieving speeds up to 500 times faster than traditional CPU-based solvers, but also reduces the potential for human error by automating data transfer and setup. Designers can now perform comprehensive device optimizations and system-level analyses entirely within the Cadence ecosystem, significantly enhancing productivity and design accuracy.

In this presentation, we will demonstrate the capabilities of the PhotonForge Connector, showcasing its impact on streamlining electronic-photonic design workflows.

Texas Instruments

Cadence’s Electrical Equivalent net, referred to as “EEnet”, gives designers the ability to model interactions between modules by passing voltage or current along with the impedance value. Users can develop these EEnet models with declared EEnet pins that can be accurate without sacrificing performance. However, when dealing with extensive mixed-signal designs that incorporate numerous UDN/EEnet instances, the challenge of debugging extended simulation times becomes more prominent. 

The UDN Profiler allows Verification Engineers to effectively monitor key areas of activity within their schematics, particularly when managing extended simulation durations in mixed-signal designs. The Profiler significantly improves the efficiency and organization of the debugging process by giving users a comprehensive overview of critical areas within their designs. Furthermore, users can identify which nets exhibit high levels of activity, and by utilizing the “Tracecode” TCL script, they can pinpoint section of their EEnet model code that are being executed. This capability is beneficial for designers aiming to develop new models or to diagnose areas where the simulator engine is struggling. 

In the example presented, we initially utilize the Profiler tool to compile a list of the most active EEnets. Subsequently, we call upon the Tracecode to identify the specific lines executed by the simulator, aiming to identify the segments of code that are taking too long to resolve.

To conclude, while EEnets offer precise simulation outcomes without the drawbacks of extended simulation durations, the performance may decline as designs become more complex, However, with the introduction of the Profiler and the Tracecode script, designers are equipped with enhanced tools for debugging schematics and custom EEnet models.

Samsung

Abstract- Coherency verification plays a pivotal role in ensuring the integrity and performance of the multiple die designs using UCIe (Universal Chiplet Interconnect Express) protocol. As multi-die/multi-chiplet system grows in complexity, keeping a consistent view of shared data across different chiplets or dies becomes increasingly challenging. Coherency ensures that no die contains stale or incorrect information. It also ensures safeguarding system stability and prevents critical issues like data corruption or race conditions. In a homogeneous/heterogeneous multi-chiplet system in package (SIP), each of the processor cores may read and write to a unified memory space. To offer a coherent view of memory in such a system, certain rules about memory reads and writes and how they act upon memory are needed. The multi-chip SIP is nowhere an exception to this mandate. To maintain the memory consistency rules across the dies, the coherency extensions provided by the ARM-based AMBA CHI (coherent hub interface) protocol help stream system traffic over the UCIe interconnect.

To accelerate interconnect verification, this paper proposes a special UCIe Verification IP (VIP) that is “sandwiched” with streaming protocol VIP and coherent VIPs forming "UCIe VIP sub-system" to achieve verification of system-level coherency even before the complete multi-chip RTL/design environment is ready. The VIP Is highly configurable and it can communicate either directly through Credited eXtensible Stream (CXS) (bypassing UCIe) or through UCIe. This unique utility provides a great head start to verification by allowing test case execution at different stages of RTL.

Akeana

Akeana, a startup developing high-performance RISC-V processor IP, faced time-to-market challenges in bringing a broad IP portfolio with highly configurable designs to market. To optimize development cycles and accelerate verification, Akeana adopted an integrated approach to simulation, emulation, and debugging utilizing Cadence's comprehensive verification solution. With Cadence's Xcelium Logic Simulator, Palladium Emulation Cloud, and Verisium Debug, Akeana amplified the output of its startup-sized engineering team, achieving remarkable results. 

This presentation will delve into the innovative verification methodology Akeana developed around Cadence's verification ecosystem, showcasing how the combination of these tools enabled rapid design cycle optimization, reduced manual debugging overhead, and accelerated time-to-market for their high-performance RISC-V IP.

Celestial AI

Celestial AI develops optical interconnect solutions for AI workloads, enhancing compute efficiency with high-bandwidth, low-latency technology.  Using a single threaded, monolithic build that required a full re-elaboration for every code change was too slow so we moved to using parallel compilation and MSIE. These technologies are a key advantage of the Xcelium simulator.

Celestial AI collaborated with Cadence to optimize the simulation performance of Xcelium. The first improvement was enabling parallel compilation using multi-threading, reducing the time of builds by 10%. Next, the DUT and verification environment were partitioned, eliminating unnecessary re-elaboration of the DUT when making testbench modifications. Finally, Celestial AI deployed Xcelium’s Multi-Snapshot Incremental Elaboration (MSIE), allowing testbench changes to be processed incrementally rather than requiring a full rebuild.

The results were significant. The optimized flow reduced testbench change build time from 30 minutes to 3 minutes. Verification engineers iterate faster improving productivity and debugging efficiency.

Ignitarium 

Jasper Formal Scoreboard is a feature within Cadence JasperGold Formal Verification Platform, which is widely used in the hardware design industry for formal verification tasks. Formal scoreboard exhaustively verifies the data integrity of data path designs. Checking for data transmission to the correct slave ensures that decoding has no errors. These checkers ensure data is not lost, re-ordered, corrupted or duplicated during transmission through the fabric and the correct slave receives the data. Before formal scoreboard comes into existence the formal verification engineers uses the FPV (formal property verification) app to write the manual user assertions to verify data integrity on the fabric design.

Jasper Formal Scoreboard automates the process of verifying that the design output matches the expected outcomes over complex sequences of operations. This end-to-end verification ensures that the overall functionality of the design is correct without the need for manually writing detailed properties for each scenario.

Compared to traditional formal verification methods that require detailed and specific property assertions, the Jasper Formal Scoreboard simplifies the setup. Users can often specify a high-level reference model or golden reference for the expected behavior, and the tool automatically generates the necessary checks and comparisons.

Jasper Formal Scoreboard supports high-level abstraction, making it easier to verify complex designs where traditional low-level properties might be difficult to define. This allows for more exhaustive verification of high-level behaviors and interactions within the design. 

The automated nature of the formal scoreboard reduces the overall time required for verification. With less manual effort required to define and manage assertions, verification engineers can achieve quicker results, speeding up the verification process and allowing earlier bug detection.

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

Designer’s Guide and Ulkasemi

As the demand for high-performance computing system on chips increases, the importance of full-chip verification with both analog and digital subsystems cannot be overstated. Validated models of the analog form the linchpin to enable true full chip verification. Unfortunately, there are many challenges to be addressed for the model producers and for the model consumers. For the producers, these challenges include identifying who will write the models, the choice of language, how to validate that the model and schematic are equivalent, finding the engineers with the necessary skills, and reducing the cost of the overall effort. For the consumers, challenges include overcoming the inexperience of using analog models in UVM and the lack of a UVM framework for analog models. 
 
 We will explore solutions to all of these challenges. We will demonstrate a flow using the Virtuoso Platform and a tool called MiM where both a validated Verilog-AMS model and a validated SystemVerilog model are byproducts of the analog design process. This answers the question of who creates the models, eliminates the choice of language question by producing models in the two languages needed, includes running model vs. schematic (MVS) as part of the flow, and simplifies the process to ease the cost and skill set requirements. We will then demonstrate the AMSV Utility Framework that runs on the Xcelium platform. This provides a UVM framework for analog models that not only facilitates catching mixed-signal interface and digital/analog functional bugs, it also allows for the verification of real world conditions including temperature effects, parametric variations, and safety concerns.
 
In this presentation, we will illustrate our solutions by starting from an analog designer point-of-view in the Virtuoso platform and ending from the chip-level verification point-of-view on the Xcelium Platform.

NVIDIA

Maintaining high quality through verification is essential in the fast-paced hardware development world. This study delves into the transformative capabilities of Xcelium SimAI technology to significantly enhance random verification efficiency. Traditionally, random simulation runs are evenly distributed across all user-defined tests, or some arbitrary distribution of runs is given to each test based on past experience of the efficacy of the test cases. This undermines the effectiveness of verification efforts by generating a large amount of redundancy and potentially missing critical corner case scenarios. SimAI’s innovative approach introduces an intelligent allocation strategy that emphasizes critical tests and important random variables and focuses on areas where the verification effort will have the highest impact.

This refined methodology aims to raise verification efficiency, ensuring simulation runs are genuinely impactful, leading to improved coverage density and the identification of latent defects. A thorough analysis of NVidia’s nightly regressions shows impressive results across all coverage metrics: Block, Statement, Expression, Toggle, FSM, Assertions, and functional coverage through Covergroup.

When SimAI was applied to the IP testbench, it achieved excellent coverage density per compute hour results while reproducing original failures and, most importantly, uncovering seven new failures. These advancements translated to a 50% reduction in regression turnaround time (TAT) and offered 2.5 times CPU savings. Notably, Nvidia found the bug-hunting capabilities of SimAI particularly valuable, as it helped them catch bugs that had previously gone undetected. With this success, Nvidia plans to deploy SimAI across all their test benches to unleash this technology's full benefits. In addition to bug hunting, SimAI also provides various other use cases. Nightly regression performance is improved similarly, often reducing nightly compute by 3x or more. Coverage Maximization by targeting coverage holes is a further efficiency-saving feature, freeing the DV engineer time by maximizing the coverage the environment can hit before the DV engineer needs to spend time on analysis and directed test creation. 

Maintaining high quality through verification is essential in the fast-paced hardware development world. This study delves into the transformative capabilities of Xcelium SimAI tech

Cadence

FPGA prototypes enable software developers to test their code before silicon is available.  These hardware prototypes are well suited for software testing because they provide a hardware-accurate, high-speed model that can run with real stimulus.  Additionally, due to their relatively low cost-per-gate, FPGA prototypes are cost-effective to deploy for large software teams.

Software testing, like hardware verification, can be divided into unit-level and system-level.  Unit-level testing proves that base HW/SW APIs function correctly.  System-level testing exercises much more complex functions with real data over extended periods.  Running system-level tests before tape-out is how companies are shifting left both software and hardware development to find issues earlier in their schedules and fix them at a fraction of the cost.

This presentation will describe examples of how FPGA prototypes are being  leveraged to effectively develop and test software to improve the quality of a product.

Air Force Research Laboratory (AFRL) 

Commercial and government organizations today are applying digital engineering (DE) to improve efficiency, transparency, reliability, and accuracy within their system development processes. Applications and definitions of DE vary based on intended use, system element / level, lifecycle phase, and other factors. This presentation will provide an overview of potential DE use cases within the DoD that covers “low level” design and verification of electronics through high level mission analysis and highlights some of the challenges in integrating and maintaining consistency across different underlying models, assumptions, and constraints.

NVIDIA

Application-level power visibility early in the design cycle is essential to designing energy efficient chips and meeting power targets. In this presentation, nVidia will share challenges associated with estimating power for real application workloads and how next generation of Palladium DPA innovation has accelerated SoC power estimation while providing a higher level of accuracy in pre-silicon environment.

Palladium Dynamic Power Analysis (DPA) offers novel technologies to estimate power of real-world scenarios spanning billions of cycles for billion gates designs in hours. Palladium’s fast dynamic power analysis enables identification of power-hotspots in the design and provides insights into power efficiency of application software and hardware interaction.

Analog Devices

As low-power ASICs continue advancing wearables and medical devices, achieving longer battery life and efficient performance is crucial. However, early-stage power estimation remains a challenge. While simulation-based power analysis provides waveforms for smaller testcases, it often takes long time to enable and run time consuming testcases , leading to longer time in generating power numbers and activity profile. To address this, we leveraged Cadence Palladium™ Z2 and Dynamic Power Analysis (DPA)to run longer simulation in less time and analyze activity profile and power consumption during early stages of design. By using Palladium’s high-speed emulation, we are to identify  power-hungry operations across key subsystems—DSP, NNE, memory, and sensor interfaces—allowing for smarter power management strategies. This ensures energy-efficient ASICs with extended battery life, delivering reliable performance for next-generation low-power devices. 

In this presentation, we will demonstrate how Palladium Z2 accelerates Deep learning based  high computing operations with, providing high performance and power visibility that traditional simulation methods take longer time to achieve. By capturing cycle-accurate switching activity, we integrated this data into Cadence Joules for precise power estimation. The results were remarkable—our power estimations were 95% accurate compared to simulation-based Joules runs, significantly increasing confidence in power numbers generated through waveforms dumped through palladium. The Power Activity Profile from DPA allowed us to evaluate toggling activity  across different components, optimize dynamic power, and implement power-saving techniques like clock gating and voltage scaling well before silicon validation. Additionally, early detection of power-hungry operations helped mitigate thermal issues and battery constraints, ensuring our ASIC met performance and efficiency goals. 

Integrating Palladium DPA into our workflow has been greatly helpful  in early-stage power estimation and optimization. By enabling real-world workload execution, we significantly improved our ability to identify inefficiencies, optimize power consumption, and enhance battery life—all before silicon validation. As low-power ASICs continue driving innovation in wearables and medical devices, leveraging hardware emulation for power analysis will be essential in meeting performance, power, and reliability goals.

Cadence

In the rapidly evolving world of chip design, the integration of Agentic AI has the potential to empower engineers to overcome complex challenges, optimize performance, and accelerate time-to-market, ushering in a new era of design excellence. During this presentation Cadence R&D will give an insight into the latest advancements in Generative AI tools, and the future trajectory of Agentic AI in semiconductor design.

GUC

GUC’s HBM4 Controller/PHY IP delivers high utilization, low latency, high-speed performance, and multi-vendor compatibility, while supporting a comprehensive set of advanced features, including QoS engines, cache-like microarchitecture, and etc. Given the complexity of these features and the diverse test scenarios required—whether at the IP or SoC level—design verification for memory controller IP remains a significant technical challenge.

Beyond verifying the HBM controller IP in a simulation environment, as well as the adoption of a Palladium emulation platform at the SoC level for validating both the memory IP and the overall memory subsystem has become an industry-standard approach, recognized for its scalability and proven effectiveness. Over the years, GUC has successfully employed this dual-methodology strategy to ensure the robustness and reliability of its HBM IP solutions.

As GUC continues to pursue excellence and optimize the efficiency of HBM design verification, we have introduced a third methodology: the Testbench-Acceleration (TBA) environment at the IP level. This approach enables earlier coverage closure and significantly enhances operational efficiency. 

Additionally, with enhancements to the HBM MMP model—jointly developed by GUC and Cadence—users can now verify HBM features more efficiently compared to traditional verification flows. In this presentation, we will demonstrate how we rapidly deploy the TBA environment by maximizing reuse and leveraging existing solutions in both simulation and emulation environments. User will gain more comprehensive results for cross-platform comparisons, enabling detailed analysis of design behavior. This strategic approach enables GUC to deliver high-quality HBM3, HBM3e, and HBM4 solutions to end customers with exceptional reliability and performance.

Cadence

In the recent years, there has been significant growth in semiconductor design activity and forecasts indicate this trend to only increase in the future. RTL design and verification are key challenges in the semiconductor design cycle and acceleration via emulation has been predominant in the industry for decades, however, the adoption of this technology has primarily catered to the needs of large-scale ‘billion-gate’ class designs in recent years.

There are design teams that create IP or small-scale yet mission critical ASIC/SoC designs across organizations that strive to enable emulation to accelerate their D&V process but existing enterprise-based emulators in the industry are typically out of reach for these users due to a variety of reasons such as limited capital budget, low priority in resource allocation, or small companies that lack the data center infrastructure to house these large-scale emulators. 

To reduce the barrier of adoption, Cadence is introducing a solution to address this market demand – Palladium Z3 System Studio. It is a stand-alone emulation appliance tailored for emulating designs of up to 128 million gates. In this session, we intend to present the benefits and features of Palladium Z3 System Studio, a leading-edge emulation appliance lowering the adoption barrier significantly for D&V teams to accelerate their hardware/software co-verification workloads.